From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTthA-0002Ba-1H for qemu-devel@nongnu.org; Thu, 11 Feb 2016 11:02:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aTth5-000862-6S for qemu-devel@nongnu.org; Thu, 11 Feb 2016 11:02:15 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:33710) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aTth5-00084g-0Q for qemu-devel@nongnu.org; Thu, 11 Feb 2016 11:02:11 -0500 From: Bastian Koppelmann Date: Thu, 11 Feb 2016 17:01:57 +0100 Message-Id: <1455206520-6465-3-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1455206520-6465-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1455206520-6465-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 2/5] target-tricore: Save the pc before CSA operations for exceptions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Exceptions that can occur during CSA operations need the PC as the return address of the exception. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 721878d..775d4c6 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3336,6 +3336,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; case OPC1_32_B_CALL: case OPC1_16_SB_CALL: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_1arg(call, ctx->next_pc); gen_goto_tb(ctx, 0, ctx->pc + offset * 2); break; @@ -3408,6 +3410,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, break; case OPC2_32_SYS_RET: case OPC2_16_SR_RET: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_ret(cpu_env); tcg_gen_exit_tb(0); break; @@ -3782,6 +3786,8 @@ static void decode_sc_opc(DisasContext *ctx, int op1) tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); break; case OPC1_16_SC_BISR: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_1arg(bisr, const16 & 0xff); break; case OPC1_16_SC_LD_A: @@ -3897,6 +3903,8 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) gen_compute_branch(ctx, op2, 0, 0, 0, 0); break; case OPC2_16_SR_RFE: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_rfe(cpu_env); tcg_gen_exit_tb(0); ctx->bstate = BS_BRANCH; @@ -7895,6 +7903,8 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) gen_fret(ctx); break; case OPC2_32_SYS_RFE: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_rfe(cpu_env); tcg_gen_exit_tb(0); ctx->bstate = BS_BRANCH; @@ -7917,9 +7927,13 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) } break; case OPC2_32_SYS_RSLCX: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_rslcx(cpu_env); break; case OPC2_32_SYS_SVLCX: + /* save pc for the exception return address */ + gen_save_pc(ctx->pc); gen_helper_svlcx(cpu_env); break; case OPC2_32_SYS_RESTORE: -- 2.7.1