From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aUEq8-0000Nx-0D for qemu-devel@nongnu.org; Fri, 12 Feb 2016 09:36:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aUEq3-0002eK-C1 for qemu-devel@nongnu.org; Fri, 12 Feb 2016 09:36:55 -0500 From: "Edgar E. Iglesias" Date: Fri, 12 Feb 2016 15:33:57 +0100 Message-Id: <1455287642-28166-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1455287642-28166-1-git-send-email-edgar.iglesias@gmail.com> References: <1455287642-28166-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 4/9] target-arm: Add more fields to the data abort syndrome generator List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, qemu-arm@nongnu.org, alex.bennee@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Add the following flags to the data abort syndrome generator: * isv - Instruction syndrome valid * sas - Syndrome access size * sse - Syndrome sign extend * srt - Syndrome register transfer * sf - Sixty-Four bit register width * ar - Acquire/Release These flags are not yet used, so this patch has no functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/internals.h | 16 ++++++++++++++-- target-arm/op_helper.c | 8 ++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/target-arm/internals.h b/target-arm/internals.h index b1c483b..0934709 100644 --- a/target-arm/internals.h +++ b/target-arm/internals.h @@ -359,13 +359,25 @@ static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | (ea << 9) | (s1ptw << 7) | fsc; } -static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw, +static inline uint32_t syn_data_abort(int same_el, int isv, + int sas, int sse, int srt, + int sf, int ar, + int ea, int cm, int s1ptw, int wnr, int fsc, bool is_thumb) { - return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) + uint32_t v; + + v = (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | (is_thumb ? 0 : ARM_EL_IL) | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc; + + /* Insn Syndrome fields are RES0 if ISV is unset. */ + if (isv) { + v |= (isv << 24) | (sas << 22) | (sse << 21) | (srt << 16) + | (sf << 15) | (ar << 14); + } + return v; } static inline uint32_t syn_swstep(int same_el, int isv, int ex) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 4e629e1..9bf635f 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -115,7 +115,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn); exc = EXCP_PREFETCH_ABORT; } else { - syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn, + syn = syn_data_abort(same_el, + 0, 0, 0, 0, 0, 0, + 0, 0, fi.s1ptw, is_write == 1, syn, env->thumb); if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { fsr |= (1 << 11); @@ -162,7 +164,9 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, } raise_exception(env, EXCP_DATA_ABORT, - syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21, + syn_data_abort(same_el, + 0, 0, 0, 0, 0, 0, + 0, 0, 0, is_write == 1, 0x21, env->thumb), target_el); } -- 1.9.1