From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52754) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aUFhQ-0002js-G0 for qemu-devel@nongnu.org; Fri, 12 Feb 2016 10:32:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aUFhP-0000oa-KB for qemu-devel@nongnu.org; Fri, 12 Feb 2016 10:32:00 -0500 From: Peter Maydell Date: Fri, 12 Feb 2016 15:31:55 +0000 Message-Id: <1455291115-30305-5-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1455291115-30305-1-git-send-email-peter.maydell@linaro.org> References: <1455291115-30305-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 4/4] target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Sergey Fedorov , qemu-arm@nongnu.org, patches@linaro.org Make get_r13_banked() raise an exception at runtime for the corner case of SRS from System mode, so that we can UNDEF it; this brings us in to line with the ARM ARM's set of permitted CONSTRAINED UNPREDICTABLE choices. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Reviewed-by: Edgar E. Iglesias --- target-arm/op_helper.c | 8 ++++++++ target-arm/translate.c | 9 +++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index cfdbc8d..538887c 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -468,6 +468,14 @@ void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) { + if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) { + /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF. + * Other UNPREDICTABLE and UNDEF cases were caught at translate time. + */ + raise_exception(env, EXCP_UDEF, syn_uncategorized(), + exception_target_el(env)); + } + if ((env->uncached_cpsr & CPSR_M) == mode) { return env->regs[13]; } else { diff --git a/target-arm/translate.c b/target-arm/translate.c index 7bceb05..e69145d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7590,10 +7590,7 @@ static void gen_srs(DisasContext *s, * -- not a valid mode number * -- a mode that's at a higher exception level * -- Monitor, if we are Non-secure - * For the UNPREDICTABLE cases we choose to UNDEF, except that for - * "current mode is System" we will write a garbage SPSR. - * (This is because we don't have access to our current mode here - * and would have to do a runtime check to UNDEF for System.) + * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns) { gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); @@ -7639,6 +7636,9 @@ static void gen_srs(DisasContext *s, addr = tcg_temp_new_i32(); tmp = tcg_const_i32(mode); + /* get_r13_banked() will raise an exception if called from System mode */ + gen_set_condexec(s); + gen_set_pc_im(s, s->pc - 4); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) { @@ -7688,6 +7688,7 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(tmp); } tcg_temp_free_i32(addr); + s->is_jmp = DISAS_UPDATE; } static void disas_arm_insn(DisasContext *s, unsigned int insn) -- 1.9.1