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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH 27/28] riscv: virt: Change create_fdt() to return void
Date: Mon,  5 Aug 2019 09:00:22 -0700	[thread overview]
Message-ID: <1565020823-24223-28-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1565020823-24223-1-git-send-email-bmeng.cn@gmail.com>

There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt. Other machines (sifive_u, spike)
don't do it neither.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/virt.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f662100..5935ac8 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename,
                            0x1800, 0, 0, 0x7);
 }
 
-static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
+static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     uint64_t mem_size, const char *cmdline)
 {
     void *fdt;
@@ -316,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
     }
     g_free(nodename);
-
-    return fdt;
 }
 
 
@@ -373,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine)
     size_t plic_hart_config_len;
     int i;
     unsigned int smp_cpus = machine->smp.cpus;
-    void *fdt;
 
     /* Initialize SOC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
@@ -392,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine)
         main_mem);
 
     /* create device tree */
-    fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+    create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 
     /* boot rom */
     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
@@ -411,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine)
             hwaddr end = riscv_load_initrd(machine->initrd_filename,
                                            machine->ram_size, kernel_entry,
                                            &start);
-            qemu_fdt_setprop_cell(fdt, "/chosen",
+            qemu_fdt_setprop_cell(s->fdt, "/chosen",
                                   "linux,initrd-start", start);
-            qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+            qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
                                   end);
         }
     }
-- 
2.7.4



  parent reply	other threads:[~2019-08-05 16:12 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-05 15:59 [Qemu-devel] [PATCH 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-05 15:59 ` [Qemu-devel] [PATCH 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-06  0:11   ` Alistair Francis
2019-08-05 15:59 ` [Qemu-devel] [PATCH 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-06  0:13   ` Alistair Francis
2019-08-05 15:59 ` [Qemu-devel] [PATCH 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-06  0:14   ` Alistair Francis
2019-08-05 15:59 ` [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-05 16:41   ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-08-06  0:16     ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-06  0:17   ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses Bin Meng
2019-08-05 16:44   ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-08-06  0:19   ` [Qemu-devel] " Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-06  0:18   ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-06  0:18   ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 16/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 17/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-06  0:20   ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 22/28] riscv: sifive_u: Generate an aliases node in the device tree Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place Bin Meng
2019-08-06  0:25   ` Alistair Francis
2019-08-05 16:00 ` [Qemu-devel] [PATCH 24/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 25/28] riscv: sifive_u: Support loading initramfs Bin Meng
2019-08-05 16:00 ` [Qemu-devel] [PATCH 26/28] riscv: hw: Update PLIC device tree Bin Meng
2019-08-05 17:00   ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-08-05 16:00 ` Bin Meng [this message]
2019-08-05 16:00 ` [Qemu-devel] [PATCH 28/28] riscv: sifive_u: Update model and compatible strings in " Bin Meng
2019-08-06  0:22   ` Alistair Francis

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