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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH for 4.2 v7 20/26] target/mips: Clean up handling of CP0 register 20
Date: Fri,  9 Aug 2019 14:46:53 +0200	[thread overview]
Message-ID: <1565354819-1495-21-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 20.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index ea2d4b1..fb62ed8 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7388,7 +7388,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_20:
         switch (sel) {
-        case 0:
+        case CP0_REG20__XCONTEXT:
 #if defined(TARGET_MIPS64)
             check_insn(ctx, ISA_MIPS3);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8127,7 +8127,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_20:
         switch (sel) {
-        case 0:
+        case CP0_REG20__XCONTEXT:
 #if defined(TARGET_MIPS64)
             check_insn(ctx, ISA_MIPS3);
             gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8872,7 +8872,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_20:
         switch (sel) {
-        case 0:
+        case CP0_REG20__XCONTEXT:
             check_insn(ctx, ISA_MIPS3);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
             register_name = "XContext";
@@ -9593,7 +9593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_20:
         switch (sel) {
-        case 0:
+        case CP0_REG20__XCONTEXT:
             check_insn(ctx, ISA_MIPS3);
             gen_helper_mtc0_xcontext(cpu_env, arg);
             register_name = "XContext";
-- 
2.7.4



  parent reply	other threads:[~2019-08-09 12:56 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-09 12:46 [Qemu-devel] [PATCH for 4.2 v7 00/26] target/mips: Misc patches for 4.2 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 01/26] target/mips: Add support for DSPRAM Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 02/26] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 03/26] target/mips: Amend CP0 MemoryMapID " Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 04/26] target/mips: Add support for emulation of GINVT instruction Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 05/26] target/mips: Add support for emulation of CRC32 group of instructions Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 06/26] target/mips: Style improvements in cp0_timer.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 07/26] target/mips: Style improvements in cpu.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 08/26] target/mips: Style improvements in helper.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 09/26] target/mips: Style improvements in internal.h Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 10/26] target/mips: Style improvements in machine.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 11/26] target/mips: Style improvements in cps.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 12/26] target/mips: Style improvements in mips_fulong2e.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 13/26] target/mips: Style improvements in mips_int.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 14/26] target/mips: Style improvements in mips_malta.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 15/26] target/mips: Style improvements in mips_mipssim.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 16/26] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 17/26] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 18/26] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 19/26] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-09 12:46 ` Aleksandar Markovic [this message]
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 21/26] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 22/26] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 23/26] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 24/26] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 25/26] target/mips: tests/tcg: Add optional printing of more detailed failure info Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 26/26] target/mips: tests/tcg: Fix target configurations for MSA tests Aleksandar Markovic

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