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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine
Date: Sun, 18 Aug 2019 22:11:45 -0700
Message-ID: <1566191521-7820-13-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com>

Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.

Note the file header says the RISC-V hart array holds the state
of a heterogeneous array of RISC-V harts, which is not true.
Update the comment to mention homogeneous array of RISC-V harts.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 hw/riscv/riscv_hart.c | 33 ++++++++++++++++++++-------------
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index ca69a1b..9deef869 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -3,7 +3,7 @@
  *
  * Copyright (c) 2017 SiFive, Inc.
  *
- * Holds the state of a heterogenous array of RISC-V harts
+ * Holds the state of a homogeneous array of RISC-V harts
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -37,26 +37,33 @@ static void riscv_harts_cpu_reset(void *opaque)
     cpu_reset(CPU(cpu));
 }
 
+static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
+                               char *cpu_type, Error **errp)
+{
+    Error *err = NULL;
+
+    object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
+                            sizeof(RISCVCPU), cpu_type,
+                            &error_abort, NULL);
+    s->harts[idx].env.mhartid = idx;
+    qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
+    object_property_set_bool(OBJECT(&s->harts[idx]), true,
+                             "realized", &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+}
+
 static void riscv_harts_realize(DeviceState *dev, Error **errp)
 {
     RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
-    Error *err = NULL;
     int n;
 
     s->harts = g_new0(RISCVCPU, s->num_harts);
 
     for (n = 0; n < s->num_harts; n++) {
-        object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
-                                sizeof(RISCVCPU), s->cpu_type,
-                                &error_abort, NULL);
-        s->harts[n].env.mhartid = n;
-        qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
-        object_property_set_bool(OBJECT(&s->harts[n]), true,
-                                 "realized", &err);
-        if (err) {
-            error_propagate(errp, err);
-            return;
-        }
+        riscv_hart_realize(s, n, s->cpu_type, errp);
     }
 }
 
-- 
2.7.4



  parent reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19  5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-19 20:08   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-19  5:11 ` Bin Meng [this message]
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-22 22:40   ` Alistair Francis
2019-08-23  1:57     ` Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-19 20:21   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-19 20:22   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-20 18:26   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-22 22:41   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-22 22:39   ` Alistair Francis
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng

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