From: guoren@kernel.org
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com,
alistair.francis@wdc.com, Guo Ren <ren_guo@c-sky.com>,
bmeng.cn@gmail.com
Subject: [PATCH V6] target/riscv: Ignore reserved bits in PTE for RV64
Date: Thu, 26 Sep 2019 08:14:21 +0800 [thread overview]
Message-ID: <1569456861-8502-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <ren_guo@c-sky.com>
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/cpu_helper.c | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
Changelog V6:
- Add Reviewer: Alistair Francis
Changelog V5:
- Add Reviewer and Tester: Bin Meng
Changelog V4:
- Change title to Ignore not Bugfix
- Use PTE_PPN_MASK for RV32 and RV64
Changelog V3:
- Use UUL define for PTE_RESERVED
- Keep ppn >> PTE_PPN_SHIFT
Changelog V2:
- Bugfix pte destroyed cause boot fail
- Change to AND with a mask instead of shifting both directions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e998348..399c2c6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -473,6 +473,13 @@
/* Page table PPN shift amount */
#define PTE_PPN_SHIFT 10
+/* Page table PPN mask */
+#if defined(TARGET_RISCV32)
+#define PTE_PPN_MASK 0xffffffffUL
+#elif defined(TARGET_RISCV64)
+#define PTE_PPN_MASK 0x3fffffffffffffULL
+#endif
+
/* Leaf page shift amount */
#define PGSHIFT 12
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..9961b37 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -261,7 +261,7 @@ restart:
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
#endif
- hwaddr ppn = pte >> PTE_PPN_SHIFT;
+ hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
if (!(pte & PTE_V)) {
/* Invalid PTE */
--
2.7.4
next reply other threads:[~2019-09-26 0:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 0:14 guoren [this message]
2019-10-12 17:33 ` [PATCH V6] target/riscv: Ignore reserved bits in PTE for RV64 Palmer Dabbelt
2019-10-13 0:16 ` Guo Ren
2019-10-13 0:33 ` Jonathan Behrens
2019-10-14 22:50 ` Alistair Francis
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