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From: Cathy Zhang <cathy.zhang@intel.com>
To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com
Cc: qemu-devel@nongnu.org, Cathy Zhang <cathy.zhang@intel.com>
Subject: [PATCH 0/3] Add CPU model for intel processor Cooper Lake
Date: Sat, 12 Oct 2019 15:00:35 +0800
Message-ID: <1570863638-22272-1-git-send-email-cathy.zhang@intel.com> (raw)

This patchset is to add CPU model for intel processor Cooper Lake. It 
will inherit features from the existing CPU model Cascadelake-Server, 
meanwhile, add the platform associated new instruction and feature
for speculative execution which the host supports. There are associated
feature bit and macro defined here as needed. 

Cathy Zhang (3):
  i386: Add MSR feature bit for MDS-NO
  i386: Add macro for stibp
  i386: Add new CPU model Cooperlake

 target/i386/cpu.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 target/i386/cpu.h |  2 ++
 2 files changed, 61 insertions(+)

-- 
1.8.3.1



             reply index

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-12  7:00 Cathy Zhang [this message]
2019-10-12  7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
2019-10-12  7:00 ` [PATCH 2/3] i386: Add macro for stibp Cathy Zhang
2019-10-12  7:00 ` [PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
2019-10-12 15:04 ` [PATCH 0/3] Add CPU model for intel processor Cooper Lake no-reply

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