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* [PATCH 0/3] Add CPU model for intel processor Cooper Lake
@ 2019-10-12  7:00 Cathy Zhang
  2019-10-12  7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Cathy Zhang @ 2019-10-12  7:00 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: qemu-devel, Cathy Zhang

This patchset is to add CPU model for intel processor Cooper Lake. It 
will inherit features from the existing CPU model Cascadelake-Server, 
meanwhile, add the platform associated new instruction and feature
for speculative execution which the host supports. There are associated
feature bit and macro defined here as needed. 

Cathy Zhang (3):
  i386: Add MSR feature bit for MDS-NO
  i386: Add macro for stibp
  i386: Add new CPU model Cooperlake

 target/i386/cpu.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 target/i386/cpu.h |  2 ++
 2 files changed, 61 insertions(+)

-- 
1.8.3.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] i386: Add MSR feature bit for MDS-NO
  2019-10-12  7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
@ 2019-10-12  7:00 ` Cathy Zhang
  2019-10-12  7:00 ` [PATCH 2/3] i386: Add macro for stibp Cathy Zhang
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Cathy Zhang @ 2019-10-12  7:00 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: qemu-devel, Cathy Zhang

Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 target/i386/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eaa5395..e757149 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -777,6 +777,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define MSR_ARCH_CAP_RSBA       (1U << 2)
 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
 #define MSR_ARCH_CAP_SSB_NO     (1U << 4)
+#define MSR_ARCH_CAP_MDS_NO     (1U << 5)
 
 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
 
-- 
1.8.3.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/3] i386: Add macro for stibp
  2019-10-12  7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
  2019-10-12  7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
@ 2019-10-12  7:00 ` Cathy Zhang
  2019-10-12  7:00 ` [PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
  2019-10-12 15:04 ` [PATCH 0/3] Add CPU model for intel processor Cooper Lake no-reply
  3 siblings, 0 replies; 5+ messages in thread
From: Cathy Zhang @ 2019-10-12  7:00 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: qemu-devel, Cathy Zhang

stibp feature is already added through the following commit.
https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955

Add a macro for it to allow CPU models report it when host supports.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 target/i386/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e757149..c47bcb5 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -717,6 +717,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
+#define CPUID_7_0_EDX_STIBP     (1U << 27) /* Single Thread Indirect Branch Predictors */
 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/
 #define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)  /*Core Capability*/
 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
-- 
1.8.3.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 3/3] i386: Add new CPU model Cooperlake
  2019-10-12  7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
  2019-10-12  7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
  2019-10-12  7:00 ` [PATCH 2/3] i386: Add macro for stibp Cathy Zhang
@ 2019-10-12  7:00 ` Cathy Zhang
  2019-10-12 15:04 ` [PATCH 0/3] Add CPU model for intel processor Cooper Lake no-reply
  3 siblings, 0 replies; 5+ messages in thread
From: Cathy Zhang @ 2019-10-12  7:00 UTC (permalink / raw)
  To: pbonzini, rth, ehabkost; +Cc: qemu-devel, Cathy Zhang

Cooper Lake is intel's successor to Cascade Lake, the new
CPU model inherits features from Cascadelake-Server, while
add one platform associated new feature: AVX512_BF16, and
STIBP for speculative execution.

Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 target/i386/cpu.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 44f1bbd..be86686 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2612,6 +2612,65 @@ static X86CPUDefinition builtin_x86_defs[] = {
         }
     },
     {
+        .name = "Cooperlake",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_INTEL,
+        .family = 6,
+        .model = 85,
+        .stepping = 10,
+        .features[FEAT_1_EDX] =
+            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
+            CPUID_DE | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
+            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
+            CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
+            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 
+            CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
+            CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
+            CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_PKU |
+            CPUID_7_0_ECX_AVX512VNNI,
+        .features[FEAT_7_0_EDX] =
+            CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
+            CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 
+        .features[FEAT_ARCH_CAPABILITIES] =
+            MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
+            MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
+        .features[FEAT_7_1_EAX] =
+            CPUID_7_1_EAX_AVX512_BF16,
+        /* Missing: XSAVES (not supported by some Linux versions,
+                * including v4.1 to v4.12).
+                * KVM doesn't yet expose any XSAVES state save component,
+                * and the only one defined in Skylake (processor tracing)
+                * probably will block migration anyway.
+                */
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .xlevel = 0x80000008,
+        .model_id = "Intel Xeon Processor (Cooperlake)",
+    },
+    {
         .name = "Icelake-Client",
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
-- 
1.8.3.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 0/3] Add CPU model for intel processor Cooper Lake
  2019-10-12  7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
                   ` (2 preceding siblings ...)
  2019-10-12  7:00 ` [PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
@ 2019-10-12 15:04 ` no-reply
  3 siblings, 0 replies; 5+ messages in thread
From: no-reply @ 2019-10-12 15:04 UTC (permalink / raw)
  To: cathy.zhang; +Cc: qemu-devel, pbonzini, cathy.zhang, ehabkost, rth

Patchew URL: https://patchew.org/QEMU/1570863638-22272-1-git-send-email-cathy.zhang@intel.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH 0/3] Add CPU model for intel processor Cooper Lake
Type: series
Message-id: 1570863638-22272-1-git-send-email-cathy.zhang@intel.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
c16a74f i386: Add new CPU model Cooperlake
c70bdd0 i386: Add macro for stibp
073abd3 i386: Add MSR feature bit for MDS-NO

=== OUTPUT BEGIN ===
1/3 Checking commit 073abd367191 (i386: Add MSR feature bit for MDS-NO)
2/3 Checking commit c70bdd0665f0 (i386: Add macro for stibp)
WARNING: line over 80 characters
#23: FILE: target/i386/cpu.h:720:
+#define CPUID_7_0_EDX_STIBP     (1U << 27) /* Single Thread Indirect Branch Predictors */

total: 0 errors, 1 warnings, 7 lines checked

Patch 2/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/3 Checking commit c16a74f138e1 (i386: Add new CPU model Cooperlake)
ERROR: trailing whitespace
#52: FILE: target/i386/cpu.c:2644:
+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | $

ERROR: trailing whitespace
#61: FILE: target/i386/cpu.c:2653:
+            CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, $

WARNING: Block comments use a leading /* on a separate line
#67: FILE: target/i386/cpu.c:2659:
+        /* Missing: XSAVES (not supported by some Linux versions,

WARNING: Block comments should align the * on each line
#68: FILE: target/i386/cpu.c:2660:
+        /* Missing: XSAVES (not supported by some Linux versions,
+                * including v4.1 to v4.12).

total: 2 errors, 2 warnings, 65 lines checked

Patch 3/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/1570863638-22272-1-git-send-email-cathy.zhang@intel.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-12  7:00 [PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
2019-10-12  7:00 ` [PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
2019-10-12  7:00 ` [PATCH 2/3] i386: Add macro for stibp Cathy Zhang
2019-10-12  7:00 ` [PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
2019-10-12 15:04 ` [PATCH 0/3] Add CPU model for intel processor Cooper Lake no-reply

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