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* [Bug 1863247] [NEW] AArch64 EXT instruction for V register does not clear MSB side bits
@ 2020-02-14 13:06 Kentaro Kawakami
  2020-02-14 17:51 ` [Bug 1863247] " Richard Henderson
  0 siblings, 1 reply; 2+ messages in thread
From: Kentaro Kawakami @ 2020-02-14 13:06 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

On AArch64 CPU with SVE register, there seems to be a bug in the
operation when executing EXT instruction to V registers. Bits above the
128 bits of the SVE register must be cleared to 0, but qemu-aarch64
seems to hold the value.

Example
ext v0.16b, v1.16b v2.16b, 8

After executing above instruction, (N-1) to 128 bits of z0 register must
be 0, where N is SVE register width.

** Affects: qemu
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/1863247

Title:
  AArch64 EXT instruction for V register does not clear MSB side bits

Status in QEMU:
  New

Bug description:
  On AArch64 CPU with SVE register, there seems to be a bug in the
  operation when executing EXT instruction to V registers. Bits above
  the 128 bits of the SVE register must be cleared to 0, but qemu-
  aarch64 seems to hold the value.

  Example
  ext v0.16b, v1.16b v2.16b, 8

  After executing above instruction, (N-1) to 128 bits of z0 register
  must be 0, where N is SVE register width.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1863247/+subscriptions


^ permalink raw reply	[flat|nested] 2+ messages in thread

* [Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits
  2020-02-14 13:06 [Bug 1863247] [NEW] AArch64 EXT instruction for V register does not clear MSB side bits Kentaro Kawakami
@ 2020-02-14 17:51 ` " Richard Henderson
  0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2020-02-14 17:51 UTC (permalink / raw)
  To: qemu-devel

Yep.

** Changed in: qemu
       Status: New => In Progress

** Changed in: qemu
     Assignee: (unassigned) => Richard Henderson (rth)

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1863247

Title:
  AArch64 EXT instruction for V register does not clear MSB side bits

Status in QEMU:
  In Progress

Bug description:
  On AArch64 CPU with SVE register, there seems to be a bug in the
  operation when executing EXT instruction to V registers. Bits above
  the 128 bits of the SVE register must be cleared to 0, but qemu-
  aarch64 seems to hold the value.

  Example
  ext v0.16b, v1.16b v2.16b, 8

  After executing above instruction, (N-1) to 128 bits of z0 register
  must be 0, where N is SVE register width.

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1863247/+subscriptions


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-02-14 13:06 [Bug 1863247] [NEW] AArch64 EXT instruction for V register does not clear MSB side bits Kentaro Kawakami
2020-02-14 17:51 ` [Bug 1863247] " Richard Henderson

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