From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A9EC2BA83 for ; Fri, 14 Feb 2020 18:02:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4DE7C20848 for ; Fri, 14 Feb 2020 18:02:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4DE7C20848 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=twiddle.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fIX-0000wP-FH for qemu-devel@archiver.kernel.org; Fri, 14 Feb 2020 13:02:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58017) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2fH3-0007FR-5O for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:01:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2fH0-0002aP-Pn for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:01:09 -0500 Received: from indium.canonical.com ([91.189.90.7]:44172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j2fH0-0002Yg-KG for qemu-devel@nongnu.org; Fri, 14 Feb 2020 13:01:06 -0500 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.86_2 #2 (Debian)) id 1j2fGz-0006Ni-7U for ; Fri, 14 Feb 2020 18:01:05 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 313972E80C0 for ; Fri, 14 Feb 2020 18:01:05 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Fri, 14 Feb 2020 17:51:15 -0000 From: Richard Henderson To: qemu-devel@nongnu.org X-Launchpad-Notification-Type: bug X-Launchpad-Bug: product=qemu; status=In Progress; importance=Undecided; assignee=rth@twiddle.net; X-Launchpad-Bug-Information-Type: Public X-Launchpad-Bug-Private: no X-Launchpad-Bug-Security-Vulnerability: no X-Launchpad-Bug-Commenters: kawakami-k rth X-Launchpad-Bug-Reporter: Kentaro Kawakami (kawakami-k) X-Launchpad-Bug-Modifier: Richard Henderson (rth) References: <158168561076.14835.7019812774701035317.malonedeb@soybean.canonical.com> Message-Id: <158170267588.24118.3605862832730660956.malone@gac.canonical.com> Subject: [Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits X-Launchpad-Message-Rationale: Subscriber (QEMU) @qemu-devel-ml X-Launchpad-Message-For: qemu-devel-ml Precedence: bulk X-Generated-By: Launchpad (canonical.com); Revision="19413b719a8df7423ab1390528edadce9e0e4aca"; Instance="production-secrets-lazr.conf" X-Launchpad-Hash: 26476940e938761a56f362a143b48d51b32eff5a X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 91.189.90.7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Bug 1863247 <1863247@bugs.launchpad.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Yep. ** Changed in: qemu Status: New =3D> In Progress ** Changed in: qemu Assignee: (unassigned) =3D> Richard Henderson (rth) -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1863247 Title: AArch64 EXT instruction for V register does not clear MSB side bits Status in QEMU: In Progress Bug description: On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu- aarch64 seems to hold the value. Example ext v0.16b, v1.16b v2.16b, 8 After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1863247/+subscriptions