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From: Laurent Vivier <Laurent@vivier.eu>
To: qemu-devel@nongnu.org
Subject: [Bug 1863247] Re: AArch64 EXT instruction for V register does not clear MSB side bits
Date: Tue, 10 Mar 2020 09:04:37 -0000	[thread overview]
Message-ID: <158383107779.7137.468850466878321708.malone@chaenomeles.canonical.com> (raw)
In-Reply-To: 158168561076.14835.7019812774701035317.malonedeb@soybean.canonical.com

Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b


** Changed in: qemu
       Status: In Progress => Fix Committed

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https://bugs.launchpad.net/bugs/1863247

Title:
  AArch64 EXT instruction for V register does not clear MSB side bits

Status in QEMU:
  Fix Committed

Bug description:
  On AArch64 CPU with SVE register, there seems to be a bug in the
  operation when executing EXT instruction to V registers. Bits above
  the 128 bits of the SVE register must be cleared to 0, but qemu-
  aarch64 seems to hold the value.

  Example
  ext v0.16b, v1.16b v2.16b, 8

  After executing above instruction, (N-1) to 128 bits of z0 register
  must be 0, where N is SVE register width.

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  parent reply	other threads:[~2020-03-10  9:19 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 13:06 [Bug 1863247] [NEW] AArch64 EXT instruction for V register does not clear MSB side bits Kentaro Kawakami
2020-02-14 17:51 ` [Bug 1863247] " Richard Henderson
2020-03-10  9:04 ` Laurent Vivier [this message]
2020-03-25 14:29 ` Kentaro Kawakami
2020-03-25 14:55 ` Richard Henderson
2020-04-30 13:29 ` Laurent Vivier

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