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[60.241.117.97]) by smtp.gmail.com with ESMTPSA id 63sm5275949pfx.132.2020.04.03.00.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2020 00:57:15 -0700 (PDT) Date: Fri, 03 Apr 2020 17:57:09 +1000 From: Nicholas Piggin Subject: Re: [PATCH 2/5] ppc/pnv: Add support for NMI interface To: =?iso-8859-1?q?C=E9dric?= Le Goater , qemu-ppc@nongnu.org References: <20200325144147.221875-1-npiggin@gmail.com> <20200325144147.221875-3-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1585899319.9tofsl4fd9.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Mahesh Salgaonkar , qemu-devel@nongnu.org, Greg Kurz , Ganesh Goudar , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" C=C3=A9dric Le Goater's on March 26, 2020 2:38 am: > [ Please use clg@kaod.org ! ] >=20 > On 3/25/20 3:41 PM, Nicholas Piggin wrote: >> This implements the NMI interface for the PNV machine, similarly to >> commit 3431648272d ("spapr: Add support for new NMI interface") for >> SPAPR. >>=20 >> Signed-off-by: Nicholas Piggin >=20 > one minor comment, >=20 > Reviewed-by: C=C3=A9dric Le Goater >=20 >> --- >> hw/ppc/pnv.c | 30 +++++++++++++++++++++++++++++- >> 1 file changed, 29 insertions(+), 1 deletion(-) >>=20 >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index b75ad06390..671535ebe6 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -27,6 +27,7 @@ >> #include "sysemu/runstate.h" >> #include "sysemu/cpus.h" >> #include "sysemu/device_tree.h" >> +#include "sysemu/hw_accel.h" >> #include "target/ppc/cpu.h" >> #include "qemu/log.h" >> #include "hw/ppc/fdt.h" >> @@ -34,6 +35,7 @@ >> #include "hw/ppc/pnv.h" >> #include "hw/ppc/pnv_core.h" >> #include "hw/loader.h" >> +#include "hw/nmi.h" >> #include "exec/address-spaces.h" >> #include "qapi/visitor.h" >> #include "monitor/monitor.h" >> @@ -1955,10 +1957,35 @@ static void pnv_machine_set_hb(Object *obj, bool= value, Error **errp) >> } >> } >>=20 >> +static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) >> +{ >> + PowerPCCPU *cpu =3D POWERPC_CPU(cs); >> + CPUPPCState *env =3D &cpu->env; >> + >> + cpu_synchronize_state(cs); >> + ppc_cpu_do_system_reset(cs); >> + /* >> + * SRR1[42:45] is set to 0100 which the ISA defines as implementati= on >=20 > I see 'System Reset' in ISA 3.0 >> + * dependent. POWER processors use this for xscom triggered interru= pts, >> + * which come from the BMC or NMI IPIs. >> + */ >> + env->spr[SPR_SRR1] |=3D PPC_BIT(43); >=20 > So we could have used the skiboot SPR_SRR1_PM_WAKE_SRESET define ?=20 Ah, that's only for power-saving wakeup. But you got me to dig further and I think I've got a few things wrong here. The architectural power save wakeup due to sreset bit 43 needs to be set, probably in excp_helper.c if (msr_pow) test. case POWERPC_EXCP_RESET: /* System reset exception = */ /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { /* indicate that we resumed from power save mode */ msr |=3D 0x10000; new_msr |=3D ((target_ulong)1 << MSR_ME); } For non-power save wakeup, it's all implementation defined. POWER9 UM=20 has the table, but I got the damn bit wrong, I was probably looking in the ISA table by mistake. It's bit 44 for that case. Linux doesn't tend=20 to care about that case, but it does care about the power save wakeup case, so this patch seems to generally "work", but I'll have to fix it. Thanks, Nick =