From: Laurent Vivier <Laurent@vivier.eu>
To: qemu-devel@nongnu.org
Subject: [Bug 1851939] Re: RISC-V mstatus TSR bit not correctly implemented
Date: Thu, 30 Apr 2020 13:37:33 -0000 [thread overview]
Message-ID: <158825385367.3631.15208170450377096980.malone@chaenomeles.canonical.com> (raw)
In-Reply-To: 157331196915.22967.16737072842793038356.malonedeb@chaenomeles.canonical.com
Fixed here:
https://git.qemu.org/?p=qemu.git;a=commitdiff;h=ed5abf46b3c4
** Changed in: qemu
Status: New => Fix Released
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https://bugs.launchpad.net/bugs/1851939
Title:
RISC-V mstatus TSR bit not correctly implemented
Status in QEMU:
Fix Released
Bug description:
Hi,
since qemu 4.1.0 the TSR bit in mstatus register is supported. But it
does not allow for executing sret in m-mode.
From the RISC-V specifications:
"When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction
exception. When TSR=0, this operation is permitted in S-mode."
This means an exception should only be raised when executing in S-mode, but not in M-mode, hence you should change the condition in helper_sret (target/riscv/op_helper.c) from:
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR))
to:
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M))
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prev parent reply other threads:[~2020-04-30 14:12 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-09 15:06 [Bug 1851939] [NEW] RISC-V mstatus TSR bit not correctly implemented tm
2020-04-30 13:37 ` Laurent Vivier [this message]
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