From: Chih-Min Chao <chihmin.chao@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Chih-Min Chao <chihmin.chao@sifive.com>
Subject: [PATCH 0/3] RFC: target/riscv: add half-precision floating-point extension
Date: Tue, 11 Aug 2020 01:59:23 -0700 [thread overview]
Message-ID: <1597136381-17296-1-git-send-email-chihmin.chao@sifive.com> (raw)
The spec is a draft but required by vector extension. The reference is
availabe at
https://github.com/riscv/riscv-isa-manual/tree/zfh
The patch depends two unmerged patch set
1. extend softfloat to support int8 and alternative NaN probagapation
2. NaNBox fix
Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com>
Based-on: <20200724002807.441147-1-richard.henderson@linaro.org>
Chih-Min Chao (2):
target/riscv: add NaN-Boxing helper for half-float
target/riscv: support 'x-k' in cpu option
Kito Cheng (1):
target/riscv: Implement zfh extension
target/riscv/cpu.c | 4 +
target/riscv/cpu.h | 2 +
target/riscv/fpu_helper.c | 180 ++++++++++
target/riscv/helper.h | 34 ++
target/riscv/insn32-64.decode | 6 +
target/riscv/insn32.decode | 32 ++
target/riscv/insn_trans/trans_rvzfh.inc.c | 531 ++++++++++++++++++++++++++++++
target/riscv/internals.h | 16 +
target/riscv/translate.c | 16 +
9 files changed, 821 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzfh.inc.c
--
2.7.4
next reply other threads:[~2020-08-11 9:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-11 8:59 Chih-Min Chao [this message]
2020-08-11 8:59 ` [PATCH 1/3] target/riscv: add NaN-Boxing helper for half-float Chih-Min Chao
2020-08-11 8:59 ` [PATCH 2/3] target/riscv: Implement zfh extension Chih-Min Chao
2020-08-25 19:00 ` Alistair Francis
2020-08-11 8:59 ` [PATCH 3/3] target/riscv: support 'x-k' in cpu option Chih-Min Chao
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