From: Jacob <1905226@bugs.launchpad.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1905226] [NEW] intel-hda: stream reset bits are broken
Date: Mon, 23 Nov 2020 03:44:32 -0000 [thread overview]
Message-ID: <160610307277.21225.14284199677830070930.malonedeb@gac.canonical.com> (raw)
Public bug reported:
>From HD audio spec, section 3.3.35:
"Stream Reset (SRST): Writing a 1 causes the corresponding stream to be
reset. [...] After the stream hardware has completed sequencing into the
reset state, it will report a 1 in this bit. Software must read a 1 from
this bit to verify that the stream is in reset. Writing a 0 causes the
corresponding stream to exit reset. When the stream hardware is ready to
begin operation, it will report a 0 in this bit. Software must read a 0
from this bit before accessing any of the stream registers."
So to reset a stream I set the bit, but it never reads back as 1 so the
driver either times out or will hang forever waiting for it to become 1.
I looked into why this happens and found that as of the latest version
(8110fa1), in function intel_hda_set_st_ctl() of the
https://github.com/qemu/qemu/blob/master/hw/audio/intel-hda.c,
if (st->ctl & 0x01) {
/* reset */
dprint(d, 1, "st #%d: reset\n", reg->stream);
st->ctl = SD_STS_FIFO_READY << 24;
}
This causes the bit to immediately become set to 0 even if I write a 1,
and clearly does not meet the spec. I checked behaviour of real hardware
and it works as expected, i.e. I see the bit will become 1 and 0 when I
write to it.
** Affects: qemu
Importance: Undecided
Status: New
** Tags: intel-hda
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https://bugs.launchpad.net/bugs/1905226
Title:
intel-hda: stream reset bits are broken
Status in QEMU:
New
Bug description:
From HD audio spec, section 3.3.35:
"Stream Reset (SRST): Writing a 1 causes the corresponding stream to
be reset. [...] After the stream hardware has completed sequencing
into the reset state, it will report a 1 in this bit. Software must
read a 1 from this bit to verify that the stream is in reset. Writing
a 0 causes the corresponding stream to exit reset. When the stream
hardware is ready to begin operation, it will report a 0 in this bit.
Software must read a 0 from this bit before accessing any of the
stream registers."
So to reset a stream I set the bit, but it never reads back as 1 so
the driver either times out or will hang forever waiting for it to
become 1. I looked into why this happens and found that as of the
latest version (8110fa1), in function intel_hda_set_st_ctl() of the
https://github.com/qemu/qemu/blob/master/hw/audio/intel-hda.c,
if (st->ctl & 0x01) {
/* reset */
dprint(d, 1, "st #%d: reset\n", reg->stream);
st->ctl = SD_STS_FIFO_READY << 24;
}
This causes the bit to immediately become set to 0 even if I write a
1, and clearly does not meet the spec. I checked behaviour of real
hardware and it works as expected, i.e. I see the bit will become 1
and 0 when I write to it.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1905226/+subscriptions
next reply other threads:[~2020-11-23 3:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 3:44 Jacob [this message]
2021-05-10 4:30 ` [Bug 1905226] Re: intel-hda: stream reset bits are broken Thomas Huth
2021-07-10 4:17 ` Launchpad Bug Tracker
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