From: Joe Komlodi <joe.komlodi@xilinx.com>
To: <qemu-devel@nongnu.org>
Cc: edgari@xilinx.com
Subject: [PATCH v1 1/3] target/microblaze: Add use-non-secure property
Date: Thu, 21 Jan 2021 16:18:53 -0800 [thread overview]
Message-ID: <1611274735-303873-2-git-send-email-komlodi@xilinx.com> (raw)
In-Reply-To: <1611274735-303873-1-git-send-email-komlodi@xilinx.com>
This property is used to control the security of the following interfaces
on MicroBlaze:
M_AXI_DP - data interface
M_AXI_IP - instruction interface
M_AXI_DC - dcache interface
M_AXI_IC - icache interface
It works by enabling or disabling the use of the non_secure[3:0] signals.
Interfaces and their corresponding values are taken from:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf
page 153.
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
---
target/microblaze/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
target/microblaze/cpu.h | 11 +++++++++++
2 files changed, 57 insertions(+)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index c8e754c..accfb23 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -98,6 +98,38 @@ static bool mb_cpu_has_work(CPUState *cs)
}
#ifndef CONFIG_USER_ONLY
+static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
+{
+ MicroBlazeCPU *cpu = opaque;
+ bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
+
+ cpu->ns_axi_dp = level & en;
+}
+
+static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
+{
+ MicroBlazeCPU *cpu = opaque;
+ bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
+
+ cpu->ns_axi_ip = level & en;
+}
+
+static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
+{
+ MicroBlazeCPU *cpu = opaque;
+ bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
+
+ cpu->ns_axi_dc = level & en;
+}
+
+static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
+{
+ MicroBlazeCPU *cpu = opaque;
+ bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
+
+ cpu->ns_axi_ic = level & en;
+}
+
static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
{
MicroBlazeCPU *cpu = opaque;
@@ -248,6 +280,10 @@ static void mb_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
/* Inbound IRQ and FIR lines */
qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
+ qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
+ qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
+ qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
+ qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
#endif
}
@@ -277,6 +313,16 @@ static Property mb_properties[] = {
DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
+ /*
+ * use-non-secure enables/disables the use of the non_secure[3:0] signals.
+ * It is a bitfield where 1 = non-secure for the following bits and their
+ * corresponding interfaces:
+ * 0x1 - M_AXI_DP
+ * 0x2 - M_AXI_IP
+ * 0x4 - M_AXI_DC
+ * 0x8 - M_AXI_IC
+ */
+ DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
false),
DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index c1c2641..199cfb0 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -233,6 +233,12 @@ typedef struct CPUMBState CPUMBState;
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* use-non-secure property masks */
+#define USE_NON_SECURE_M_AXI_DP_MASK 0x1
+#define USE_NON_SECURE_M_AXI_IP_MASK 0x2
+#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
+#define USE_NON_SECURE_M_AXI_IC_MASK 0x8
+
struct CPUMBState {
uint32_t bvalue; /* TCG temporary, only valid during a TB */
uint32_t btarget; /* Full resolved branch destination */
@@ -316,6 +322,7 @@ typedef struct {
bool use_msr_instr;
bool use_pcmp_instr;
bool use_mmu;
+ uint8_t use_non_secure;
bool dcache_writeback;
bool endi;
bool dopb_bus_exception;
@@ -337,6 +344,10 @@ struct MicroBlazeCPU {
CPUState parent_obj;
/*< public >*/
+ bool ns_axi_dp;
+ bool ns_axi_ip;
+ bool ns_axi_dc;
+ bool ns_axi_ic;
CPUNegativeOffsetState neg;
CPUMBState env;
--
2.7.4
next prev parent reply other threads:[~2021-01-22 0:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-22 0:18 [PATCH v1 0/3] target/microblaze: Add memattrs on transactions Joe Komlodi
2021-01-22 0:18 ` Joe Komlodi [this message]
2021-01-26 11:16 ` [PATCH v1 1/3] target/microblaze: Add use-non-secure property Edgar E. Iglesias
2021-01-22 0:18 ` [PATCH v1 2/3] target/microblaze: use MMUAccessType instead of int in mmu_translate Joe Komlodi
2021-01-22 20:54 ` Richard Henderson
2021-01-26 11:16 ` Edgar E. Iglesias
2021-01-22 0:18 ` [PATCH v1 3/3] target/microblaze: Add security attributes on memory transactions Joe Komlodi
2021-01-26 11:16 ` Edgar E. Iglesias
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