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Thu, 21 Jan 2021 16:18:55 -0800 From: Joe Komlodi To: Subject: [PATCH v1 3/3] target/microblaze: Add security attributes on memory transactions Date: Thu, 21 Jan 2021 16:18:55 -0800 Message-ID: <1611274735-303873-4-git-send-email-komlodi@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611274735-303873-1-git-send-email-komlodi@xilinx.com> References: <1611274735-303873-1-git-send-email-komlodi@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a9bb3a2-458d-4505-75eb-08d8be6b5009 X-MS-TrafficTypeDiagnostic: PH0PR02MB7463: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2512; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Qe1m6P5vGwNFg8el9wCMlfXmvVzPf61YmPSGOIa59cVHA8JgeJ90l+tkoEtFmoJWjcMD+a9VrOlbYPsCC+kjO7kC8jCOUfJzreROtas9KN3sMs8dDJBxfQlLM1GNUlscafLwI764LVOGdEAcCocgqypDviQy1v4KAY9TlTusH+dsSExI8mhaFu2hh8zWV+rwbJ3DAgDTnU4jumTUN14uwvGhyWADUKDvux/YXoSsaEzaDMljtMPKYhmk+efrQ2q75uqqiyFi5jmt1j5voaur6Ok1Van3IK4/zadHxkDLVdFd+ToWtBOOp/1V2LKevEw0kJM6e9Fp7pk4jeq+5hnWL0vzabfARx7bhTFzSwSGJjYxoZ5inO0odPSWPGjeef0w4hR4jwHoyjid+rHzPuaFDYH5rWLpb3w/33fBTEMA46ZPdZ4R4wnUps7PhDWdrLsOofESm1CXPhDmbxhSM2YR8CLS5Zbq0Hq/xvsgv/deszWdsw+GYBMOE07DtR8DQoTi X-Forefront-Antispam-Report: CIP:149.199.62.198; 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envelope-from=komlodi@xilinx.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Using the cfg.use_non_secure bitfield and the MMU access type, we can determine if the access should be secure or not. Signed-off-by: Joe Komlodi --- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 3 ++- target/microblaze/helper.c | 26 +++++++++++++++++++++++--- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index accfb23..d5e8bfe 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -375,7 +375,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->tlb_fill = mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = mb_cpu_transaction_failed; - cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; + cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug; dc->vmsd = &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 199cfb0..e4bba8a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index cda14a1..20dbd67 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -46,6 +46,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #else /* !CONFIG_USER_ONLY */ +static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, + MMUAccessType access_type) +{ + if (access_type == MMU_INST_FETCH) { + return !cpu->ns_axi_ip; + } else { + return !cpu->ns_axi_dp; + } +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -55,12 +65,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MicroBlazeMMULookup lu; unsigned int hit; int prot; + MemTxAttrs attrs = {}; + + attrs.secure = mb_cpu_access_is_secure(cpu, access_type); if (mmu_idx == MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } @@ -71,7 +85,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } @@ -230,7 +245,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } } -hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; @@ -239,6 +255,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int mmu_idx = cpu_mmu_index(env, false); unsigned int hit; + /* Caller doesn't initialize */ + *attrs = (MemTxAttrs) {}; + attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); + if (mmu_idx != MMU_NOMMU_IDX) { hit = mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { -- 2.7.4