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From: Chris Browy <cbrowy@avery-design.com>
To: mst@redhat.com
Cc: ben.widawsky@intel.com, david@redhat.com, qemu-devel@nongnu.org,
	vishal.l.verma@intel.com, jgroves@micron.com,
	Chris Browy <cbrowy@avery-design.com>,
	armbru@redhat.com, linux-cxl@vger.kernel.org, f4bug@amsat.org,
	hchkuo@avery-design.com.tw, tyshao@avery-design.com.tw,
	jonathan.cameron@huawei.com, imammedo@redhat.com,
	dan.j.williams@intel.com, ira.weiny@intel.com
Subject: [PATCH v4 cxl-2.0-doe 0/3] QEMU PCIe DOE for PCIe and CXL2.0
Date: Wed, 31 Mar 2021 12:12:05 -0400	[thread overview]
Message-ID: <1617207125-1138-1-git-send-email-cbrowy@avery-design.com> (raw)

 Version 4 patch series for PCIe DOE for PCIe and CXL 2.0 completes
 all planned functionality.
 
 Based on QEMU version:
 https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4

Summary of changes:
 1: PCIe DOE support for Discovery
    - Fix the alignment error in DOE config write
    - Fix the interrupt disabling issue in DOE config write
    - Naming and comments clean up
	- Removed CMA support 
 2: CXL DOE for CDAT and Compliance Mode.
    - Add default values for the absence of CDAT file
    - Add cdatCDAT file example for use with cdat=<filename>
    - Refactor DOE CXL compliance mode
    - Naming and comments clean up

hchkuo (3):
  PCIe Data Object Exchange implementation
  CXL Data Object Exchange implementation
  PCIe standard header for DOE

 MAINTAINERS                               |   7 +
 hw/cxl/cxl-cdat.c                         | 220 ++++++++++++++++++
 hw/cxl/meson.build                        |   1 +
 hw/mem/cxl_type3.c                        | 200 +++++++++++++++++
 hw/pci/meson.build                        |   1 +
 hw/pci/pcie_doe.c                         | 356 ++++++++++++++++++++++++++++++
 include/hw/cxl/cxl_cdat.h                 | 149 +++++++++++++
 include/hw/cxl/cxl_compliance.h           | 297 +++++++++++++++++++++++++
 include/hw/cxl/cxl_component.h            |   7 +
 include/hw/cxl/cxl_device.h               |   4 +
 include/hw/cxl/cxl_pci.h                  |   2 +
 include/hw/pci/pci_ids.h                  |   2 +
 include/hw/pci/pcie.h                     |   1 +
 include/hw/pci/pcie_doe.h                 | 123 +++++++++++
 include/hw/pci/pcie_regs.h                |   3 +
 include/standard-headers/linux/pci_regs.h |   3 +-
 tests/data/cdat/cdat.dat                  | Bin 0 -> 148 bytes
 17 files changed, 1375 insertions(+), 1 deletion(-)
 create mode 100644 hw/cxl/cxl-cdat.c
 create mode 100644 hw/pci/pcie_doe.c
 create mode 100644 include/hw/cxl/cxl_cdat.h
 create mode 100644 include/hw/cxl/cxl_compliance.h
 create mode 100644 include/hw/pci/pcie_doe.h
 create mode 100644 tests/data/cdat/cdat.dat

-- 
1.8.3.1



             reply	other threads:[~2021-03-31 16:17 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-31 16:12 Chris Browy [this message]
2021-03-31 16:36 ` [PATCH v4 cxl-2.0-doe 1/3] PCIe Data Object Exchange implementation Chris Browy
2021-04-09 14:49   ` Jonathan Cameron
2021-03-31 16:36 ` [PATCH v4 cxl-2.0-doe 2/3] CXL " Chris Browy
2021-04-09 15:25   ` Jonathan Cameron
2021-03-31 16:37 ` [PATCH v4 cxl-2.0-doe 3/3] PCIe standard header for DOE Chris Browy
2021-04-09 15:27   ` Jonathan Cameron

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