From: Taylor Simpson <tsimpson@quicinc.com> To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Subject: [PATCH v2 04/21] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Date: Wed, 31 Mar 2021 22:53:16 -0500 [thread overview] Message-ID: <1617249213-22667-5-git-send-email-tsimpson@quicinc.com> (raw) In-Reply-To: <1617249213-22667-1-git-send-email-tsimpson@quicinc.com> When exiting a TB, generate all the code before returning from hexagon_tr_translate_packet so that nothing needs to be done in hexagon_tr_tb_stop. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> --- target/hexagon/translate.c | 62 ++++++++++++++++++++++++---------------------- target/hexagon/translate.h | 3 --- 2 files changed, 33 insertions(+), 32 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index e235fdb..9f2a531 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,16 +54,40 @@ static const char * const hexagon_prednames[] = { "p0", "p1", "p2", "p3" }; -void gen_exception(int excp) +static void gen_exception_raw(int excp) { TCGv_i32 helper_tmp = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); } -void gen_exception_debug(void) +static void gen_exec_counters(DisasContext *ctx) +{ + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], + hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], + hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); +} + +static void gen_end_tb(DisasContext *ctx) { - gen_exception(EXCP_DEBUG); + gen_exec_counters(ctx); + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + if (ctx->base.singlestep_enabled) { + gen_exception_raw(EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + ctx->base.is_jmp = DISAS_NORETURN; +} + +static void gen_exception_end_tb(DisasContext *ctx, int excp) +{ + gen_exec_counters(ctx); + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + gen_exception_raw(excp); + ctx->base.is_jmp = DISAS_NORETURN; + } #if HEX_DEBUG @@ -225,8 +249,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext *ctx, mark_implicit_writes(ctx, insn); insn->generate(env, ctx, insn, pkt); } else { - gen_exception(HEX_EXCP_INVALID_OPCODE); - ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); } } @@ -447,14 +470,6 @@ static void update_exec_counters(DisasContext *ctx, Packet *pkt) ctx->num_insns += num_real_insns; } -static void gen_exec_counters(DisasContext *ctx) -{ - tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], - hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); - tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], - hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); -} - static void gen_commit_packet(DisasContext *ctx, Packet *pkt) { gen_reg_writes(ctx); @@ -478,7 +493,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet *pkt) #endif if (pkt->pkt_has_cof) { - ctx->base.is_jmp = DISAS_NORETURN; + gen_end_tb(ctx); } } @@ -491,8 +506,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) nwords = read_packet_words(env, ctx, words); if (!nwords) { - gen_exception(HEX_EXCP_INVALID_PACKET); - ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); return; } @@ -505,8 +519,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) gen_commit_packet(ctx, &pkt); ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; } else { - gen_exception(HEX_EXCP_INVALID_PACKET); - ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); } } @@ -536,9 +549,7 @@ static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, { DisasContext *ctx = container_of(dcbase, DisasContext, base); - tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); - ctx->base.is_jmp = DISAS_NORETURN; - gen_exception_debug(); + gen_exception_end_tb(ctx, EXCP_DEBUG); /* * The address covered by the breakpoint must be included in * [tb->pc, tb->pc + tb->size) in order to for it to be @@ -601,19 +612,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_exec_counters(ctx); tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); if (ctx->base.singlestep_enabled) { - gen_exception_debug(); + gen_exception_raw(EXCP_DEBUG); } else { tcg_gen_exit_tb(NULL, 0); } break; case DISAS_NORETURN: - gen_exec_counters(ctx); - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); - if (ctx->base.singlestep_enabled) { - gen_exception_debug(); - } else { - tcg_gen_exit_tb(NULL, 0); - } break; default: g_assert_not_reached(); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 938f7fb..12506c8 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -86,8 +86,5 @@ extern TCGv hex_llsc_addr; extern TCGv hex_llsc_val; extern TCGv_i64 hex_llsc_val_i64; -void gen_exception(int excp); -void gen_exception_debug(void); - void process_store(DisasContext *ctx, Packet *pkt, int slot_num); #endif -- 2.7.4
next prev parent reply other threads:[~2021-04-01 4:00 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-01 3:53 [PATCH v2 00/21] Hexagon (target/hexagon) update Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup Taylor Simpson 2021-04-02 17:25 ` Richard Henderson 2021-04-02 17:46 ` Richard Henderson 2021-04-02 19:42 ` Taylor Simpson 2021-04-02 20:00 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 02/21] Hexagon (target/hexagon) remove unnecessary inline directives Taylor Simpson 2021-04-02 17:26 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 03/21] Hexagon (target/hexagon) use env_archcpu and env_cpu Taylor Simpson 2021-04-02 17:27 ` Richard Henderson 2021-04-01 3:53 ` Taylor Simpson [this message] 2021-04-02 17:34 ` [PATCH v2 04/21] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Richard Henderson 2021-04-01 3:53 ` [PATCH v2 05/21] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Taylor Simpson 2021-04-02 17:44 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 06/21] Hexagon (target/hexagon) change variables from int to bool when appropriate Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 07/21] Hexagon (target/hexagon) remove unused carry_from_add64 function Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 08/21] Hexagon (target/hexagon) change type of softfloat_roundingmodes Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 09/21] Hexagon (target/hexagon) use softfloat default NaN and tininess Taylor Simpson 2021-04-02 17:48 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 10/21] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 11/21] Hexagon (target/hexagon) use softfloat for float-to-int conversions Taylor Simpson 2021-04-06 20:09 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 12/21] Hexagon (target/hexagon) add F2_sfrecipa instruction Taylor Simpson 2021-04-06 20:30 ` Richard Henderson 2021-04-06 20:46 ` Richard Henderson 2021-04-06 21:55 ` Taylor Simpson 2021-04-06 22:13 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 13/21] Hexagon (target/hexagon) add F2_sfinvsqrta Taylor Simpson 2021-04-06 20:47 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 14/21] Hexagon (target/hexagon) add A5_ACS (vacsh) Taylor Simpson 2021-04-06 20:51 ` Richard Henderson 2021-04-06 21:31 ` Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 15/21] Hexagon (target/hexagon) add A6_vminub_RdP Taylor Simpson 2021-04-06 20:57 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 16/21] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Taylor Simpson 2021-04-06 21:11 ` Richard Henderson 2021-04-06 21:58 ` Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing Taylor Simpson 2021-04-06 22:11 ` Richard Henderson 2021-04-07 3:11 ` Taylor Simpson 2021-04-07 16:27 ` Taylor Simpson 2021-04-01 3:53 ` [PATCH v2 18/21] Hexagon (target/hexagon) bit reverse (brev) addressing Taylor Simpson 2021-04-06 22:35 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 19/21] Hexagon (target/hexagon) load and unpack bytes instructions Taylor Simpson 2021-04-06 22:46 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 20/21] Hexagon (target/hexagon) load into shifted register instructions Taylor Simpson 2021-04-06 22:50 ` Richard Henderson 2021-04-01 3:53 ` [PATCH v2 21/21] Hexagon (target/hexagon) CABAC decode bin Taylor Simpson 2021-04-06 22:54 ` Richard Henderson
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