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[193.116.90.211]) by smtp.gmail.com with ESMTPSA id u24sm143987pga.78.2021.04.13.20.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 20:26:46 -0700 (PDT) Date: Wed, 14 Apr 2021 13:26:40 +1000 From: Nicholas Piggin Subject: Re: [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour To: Fabiano Rosas , qemu-ppc@nongnu.org References: <20210413125448.1689545-1-npiggin@gmail.com> <20210413125448.1689545-2-npiggin@gmail.com> <87y2dm47nb.fsf@linux.ibm.com> In-Reply-To: <87y2dm47nb.fsf@linux.ibm.com> MIME-Version: 1.0 Message-Id: <1618370656.ss5qyaukyq.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?iso-8859-1?q?C=E9dric?= Le Goater , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Excerpts from Fabiano Rosas's message of April 13, 2021 11:48 pm: > Nicholas Piggin writes: >=20 >> ISA v3.0 radix guest execution has a quirk in AIL behaviour such that >> the LPCR[AIL] value can apply to hypervisor interrupts. >> >> This affects machines that emulate HV=3D1 mode (i.e., powernv9). >> >=20 > Ah ok, so we actually want to replicate the quirk in the pnv > machine. Took me a while. Yes. Quirk is probably the wrong word for me to use. It's architected=20 behaviour so it must be implemented, it's just slightly surprising / easy to miss. >=20 > Reviewed-by: Fabiano Rosas Thanks, Nick >=20 >> Signed-off-by: Nicholas Piggin >> --- >> target/ppc/excp_helper.c | 17 +++++++++++++---- >> 1 file changed, 13 insertions(+), 4 deletions(-) >> >> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >> index 85de7e6c90..b8881c0f85 100644 >> --- a/target/ppc/excp_helper.c >> +++ b/target/ppc/excp_helper.c >> @@ -791,14 +791,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, i= nt excp_model, int excp) >> #endif >> =20 >> /* >> - * AIL only works if there is no HV transition and we are running >> - * with translations enabled >> + * AIL only works if MSR[IR] and MSR[DR] are both enabled. >> */ >> - if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || >> - ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { >> + if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) { >> ail =3D 0; >> } >> =20 >> + /* >> + * AIL does not work if there is a MSR[HV] 0->1 transition and the >> + * partition is in HPT mode. For radix guests, such interrupts are >> + * allowed to be delivered to the hypervisor in ail mode. >> + */ >> + if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) { >> + if (!(env->spr[SPR_LPCR] & LPCR_HR)) { >> + ail =3D 0; >> + } >> + } >> + >> vector =3D env->excp_vectors[excp]; >> if (vector =3D=3D (target_ulong)-1ULL) { >> cpu_abort(cs, "Raised an exception without defined vector %d\n"= , >=20