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[193.116.90.211]) by smtp.gmail.com with ESMTPSA id c21sm178613pfc.165.2021.04.14.22.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Apr 2021 22:25:49 -0700 (PDT) Date: Thu, 15 Apr 2021 15:25:43 +1000 From: Nicholas Piggin Subject: Re: [EXTERNAL] [RFC PATCH 1/2] target/ppc: rework AIL logic in interrupt delivery To: =?iso-8859-1?q?C=E9dric?= Le Goater , qemu-ppc@nongnu.org References: <20210414032343.1720010-1-npiggin@gmail.com> <20210414032343.1720010-2-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1618464037.6efzvw5ldq.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabiano Rosas , =?iso-8859-1?q?C=E9dric?= Le Goater , qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Excerpts from C=C3=A9dric Le Goater's message of April 15, 2021 1:24 am: > On 4/14/21 5:23 AM, Nicholas Piggin wrote: >> The AIL logic is becoming unmanageable spread all over powerpc_excp(), >> and it is slated to get even worse with POWER10 support. >>=20 >> Move it all to a new helper function. >=20 > Reviewed-by: C=C3=A9dric Le Goater > Tested-by: C=C3=A9dric Le Goater >=20 > Thanks for the effort and the documentation. One minor comment below, >=20 > C. >=20 >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> hw/ppc/spapr_hcall.c | 3 +- >> target/ppc/cpu.h | 8 -- >> target/ppc/excp_helper.c | 161 ++++++++++++++++++++------------ >> target/ppc/translate_init.c.inc | 2 +- >> 4 files changed, 104 insertions(+), 70 deletions(-) >>=20 >> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c >> index 7b5cd3553c..2fbe04a689 100644 >> --- a/hw/ppc/spapr_hcall.c >> +++ b/hw/ppc/spapr_hcall.c >> @@ -1395,7 +1395,8 @@ static target_ulong h_set_mode_resource_addr_trans= _mode(PowerPCCPU *cpu, >> return H_P4; >> } >>=20 >> - if (mflags =3D=3D AIL_RESERVED) { >> + if (mflags =3D=3D 1) { >> + /* AIL=3D1 is reserved */ >> return H_UNSUPPORTED_FLAG; >> } >>=20 >> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h >> index e73416da68..5200a16d23 100644 >> --- a/target/ppc/cpu.h >> +++ b/target/ppc/cpu.h >> @@ -2375,14 +2375,6 @@ enum { >> HMER_XSCOM_STATUS_MASK =3D PPC_BITMASK(21, 23), >> }; >>=20 >> -/* Alternate Interrupt Location (AIL) */ >> -enum { >> - AIL_NONE =3D 0, >> - AIL_RESERVED =3D 1, >> - AIL_0001_8000 =3D 2, >> - AIL_C000_0000_0000_4000 =3D 3, >> -}; >=20 > I kind of like these. No big deal. My thinking was they actually are just a POWER8 model of the AIL bits=20 (e.g., they don't represent scv properly or AIL=3D2 reserved in P10), and=20 they spread the meaning over multiple files. After this patch it's all just in that single function. >>=20 >> - switch (ail) { >> - case AIL_NONE: >> - break; >> - case AIL_0001_8000: >> - offset =3D 0x18000; >> - break; >> - case AIL_C000_0000_0000_4000: >> - offset =3D 0xc000000000004000ull; >> - break; >> - default: >> - cpu_abort(cs, "Invalid AIL combination %d\n", ail); >=20 > Could we keep this abort ?=20 Well the abort is no longer there because we explicitly handle all=20 cases, the reserved ones by just ignoring them. I don't know what the hardware actually does if you tried to set it (it should ignore) but I think this is nicer to not abort. Thanks, Nick