* [Bug 1926277] [NEW] MIPS MT dvpe does not regard VPEConf0.MVP
@ 2021-04-27 9:19 Hansni Bu
2021-04-27 10:35 ` [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Philippe Mathieu-Daudé
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Hansni Bu @ 2021-04-27 9:19 UTC (permalink / raw)
To: qemu-devel
Public bug reported:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The MIPS®
MT Application-Specific Extension to the MIPS32® Architecture, for
instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master VPE.
Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
** Affects: qemu
Importance: Undecided
Status: New
** Tags: dvpe evpe mips mt
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
New
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE
@ 2021-04-27 10:35 ` Philippe Mathieu-Daudé
2021-04-27 10:35 ` [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP Philippe Mathieu-Daudé
0 siblings, 1 reply; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 10:35 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, 1926277, Philippe Mathieu-Daudé,
Edgar E . Iglesias, Aurelien Jarno
According to the 'MIPS MT Application-Specific Extension' manual:
If the VPE executing the instruction is not a Master VPE,
with the MVP bit of the VPEConf0 register set, the EVP bit
is unchanged by the instruction.
Add the VPEConf0.MVP bit and modify the DVPE/EVPE opcodes to only
update the MVPControl.EVP bit if executed on a master VPE.
Reported-by: Hansni Bu
Buglink: https://bugs.launchpad.net/qemu/+bug/1926277
Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 1 +
target/mips/cp0_helper.c | 32 ++++++++++++++++++--------------
2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..bd22fac6959 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -114,6 +114,7 @@ struct CPUMIPSMVPContext {
#define CP0MVPC0_PTLBE 16
#define CP0MVPC0_TCA 15
#define CP0MVPC0_PVPE 10
+#define CP0MVPC0_MVP 1
#define CP0MVPC0_PTC 0
int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM 31
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index aae2af6eccc..1e39e28808a 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- /* Turn off all VPEs except the one executing the dvpe. */
- if (&other_cpu->env != env) {
- other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu);
+ if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ /* Turn off all VPEs except the one executing the dvpe. */
+ if (&other_cpu->env != env) {
+ other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ mips_vpe_sleep(other_cpu);
+ }
}
}
return prev;
@@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- if (&other_cpu->env != env
- /* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu)) {
- /* Enable the VPE. */
- other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu); /* And wake it up. */
+ if (&other_cpu->env != env
+ /* If the VPE is WFI, don't disturb its sleep. */
+ && !mips_vpe_is_wfi(other_cpu)) {
+ /* Enable the VPE. */
+ other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ mips_vpe_wake(other_cpu); /* And wake it up. */
+ }
}
}
return prev;
--
2.26.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP
2021-04-27 10:35 ` [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Philippe Mathieu-Daudé
@ 2021-04-27 10:35 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 10:35 UTC (permalink / raw)
To: qemu-devel
According to the 'MIPS MT Application-Specific Extension' manual:
If the VPE executing the instruction is not a Master VPE,
with the MVP bit of the VPEConf0 register set, the EVP bit
is unchanged by the instruction.
Add the VPEConf0.MVP bit and modify the DVPE/EVPE opcodes to only
update the MVPControl.EVP bit if executed on a master VPE.
Reported-by: Hansni Bu
Buglink: https://bugs.launchpad.net/qemu/+bug/1926277
Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 1 +
target/mips/cp0_helper.c | 32 ++++++++++++++++++--------------
2 files changed, 19 insertions(+), 14 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..bd22fac6959 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -114,6 +114,7 @@ struct CPUMIPSMVPContext {
#define CP0MVPC0_PTLBE 16
#define CP0MVPC0_TCA 15
#define CP0MVPC0_PVPE 10
+#define CP0MVPC0_MVP 1
#define CP0MVPC0_PTC 0
int32_t CP0_MVPConf1;
#define CP0MVPC1_CIM 31
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index aae2af6eccc..1e39e28808a 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- /* Turn off all VPEs except the one executing the dvpe. */
- if (&other_cpu->env != env) {
- other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu);
+ if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ /* Turn off all VPEs except the one executing the dvpe. */
+ if (&other_cpu->env != env) {
+ other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ mips_vpe_sleep(other_cpu);
+ }
}
}
return prev;
@@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ if (env->mvp->CP0_MVPConf0 & (1 << CP0MVPC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- if (&other_cpu->env != env
- /* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu)) {
- /* Enable the VPE. */
- other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu); /* And wake it up. */
+ if (&other_cpu->env != env
+ /* If the VPE is WFI, don't disturb its sleep. */
+ && !mips_vpe_is_wfi(other_cpu)) {
+ /* Enable the VPE. */
+ other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ mips_vpe_wake(other_cpu); /* And wake it up. */
+ }
}
}
return prev;
--
2.26.3
** Changed in: qemu
Status: New => Confirmed
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
Confirmed
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP
2021-04-27 9:19 [Bug 1926277] [NEW] MIPS MT dvpe does not regard VPEConf0.MVP Hansni Bu
2021-04-27 10:35 ` [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Philippe Mathieu-Daudé
@ 2021-04-27 11:42 ` Hansni Bu
2021-04-27 13:29 ` Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Hansni Bu @ 2021-04-27 11:42 UTC (permalink / raw)
To: qemu-devel
Hi Philippe,
Instead of checking with MVPConf0, I think we should check with
VPEConf0.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
Confirmed
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP
2021-04-27 9:19 [Bug 1926277] [NEW] MIPS MT dvpe does not regard VPEConf0.MVP Hansni Bu
2021-04-27 10:35 ` [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Philippe Mathieu-Daudé
2021-04-27 11:42 ` Hansni Bu
@ 2021-04-27 13:29 ` Philippe Mathieu-Daudé
2021-04-27 13:33 ` [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Philippe Mathieu-Daudé
2021-05-09 16:16 ` [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP Philippe Mathieu-Daudé
4 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 13:29 UTC (permalink / raw)
To: qemu-devel
Oops you are right. The problem is I don't have reproducer, so I rely on
your testing :)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
Confirmed
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE
@ 2021-04-27 13:33 ` Philippe Mathieu-Daudé
2021-04-27 13:33 ` [Bug 1926277] " Philippe Mathieu-Daudé
0 siblings, 1 reply; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 13:33 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, 1926277, Philippe Mathieu-Daudé,
Edgar E . Iglesias, Aurelien Jarno
According to the 'MIPS MT Application-Specific Extension' manual:
If the VPE executing the instruction is not a Master VPE,
with the MVP bit of the VPEConf0 register set, the EVP bit
is unchanged by the instruction.
Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit
if executed on a master VPE.
Reported-by: Hansni Bu <https://launchpad.net/%7Ehansni/+contactuser>
Buglink: https://bugs.launchpad.net/qemu/+bug/1926277
Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Supersedes: <20210427103555.112652-1-f4bug@amsat.org>
v2: Check VPEConf0.MVP bit (hansni)
---
target/mips/cp0_helper.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index aae2af6eccc..d5f274f5cdf 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- /* Turn off all VPEs except the one executing the dvpe. */
- if (&other_cpu->env != env) {
- other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu);
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ /* Turn off all VPEs except the one executing the dvpe. */
+ if (&other_cpu->env != env) {
+ other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ mips_vpe_sleep(other_cpu);
+ }
}
}
return prev;
@@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- if (&other_cpu->env != env
- /* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu)) {
- /* Enable the VPE. */
- other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu); /* And wake it up. */
+ if (&other_cpu->env != env
+ /* If the VPE is WFI, don't disturb its sleep. */
+ && !mips_vpe_is_wfi(other_cpu)) {
+ /* Enable the VPE. */
+ other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ mips_vpe_wake(other_cpu); /* And wake it up. */
+ }
}
}
return prev;
--
2.26.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Bug 1926277] [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE
2021-04-27 13:33 ` [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Philippe Mathieu-Daudé
@ 2021-04-27 13:33 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-27 13:33 UTC (permalink / raw)
To: qemu-devel
According to the 'MIPS MT Application-Specific Extension' manual:
If the VPE executing the instruction is not a Master VPE,
with the MVP bit of the VPEConf0 register set, the EVP bit
is unchanged by the instruction.
Modify the DVPE/EVPE opcodes to only update the MVPControl.EVP bit
if executed on a master VPE.
Reported-by: Hansni Bu <https://launchpad.net/%7Ehansni/+contactuser>
Buglink: https://bugs.launchpad.net/qemu/+bug/1926277
Fixes: f249412c749 ("mips: Add MT halting and waking of VPEs")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Supersedes: <20210427103555.112652-1-f4bug@amsat.org>
v2: Check VPEConf0.MVP bit (hansni)
---
target/mips/cp0_helper.c | 32 ++++++++++++++++++--------------
1 file changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index aae2af6eccc..d5f274f5cdf 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -1635,12 +1635,14 @@ target_ulong helper_dvpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- /* Turn off all VPEs except the one executing the dvpe. */
- if (&other_cpu->env != env) {
- other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
- mips_vpe_sleep(other_cpu);
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ /* Turn off all VPEs except the one executing the dvpe. */
+ if (&other_cpu->env != env) {
+ other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ mips_vpe_sleep(other_cpu);
+ }
}
}
return prev;
@@ -1651,15 +1653,17 @@ target_ulong helper_evpe(CPUMIPSState *env)
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- if (&other_cpu->env != env
- /* If the VPE is WFI, don't disturb its sleep. */
- && !mips_vpe_is_wfi(other_cpu)) {
- /* Enable the VPE. */
- other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
- mips_vpe_wake(other_cpu); /* And wake it up. */
+ if (&other_cpu->env != env
+ /* If the VPE is WFI, don't disturb its sleep. */
+ && !mips_vpe_is_wfi(other_cpu)) {
+ /* Enable the VPE. */
+ other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ mips_vpe_wake(other_cpu); /* And wake it up. */
+ }
}
}
return prev;
--
2.26.3
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
Confirmed
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP
2021-04-27 9:19 [Bug 1926277] [NEW] MIPS MT dvpe does not regard VPEConf0.MVP Hansni Bu
` (3 preceding siblings ...)
2021-04-27 13:33 ` [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Philippe Mathieu-Daudé
@ 2021-05-09 16:16 ` Philippe Mathieu-Daudé
4 siblings, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-09 16:16 UTC (permalink / raw)
To: qemu-devel
This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'invalid' now.
Please continue with the discussion here:
https://gitlab.com/qemu-project/qemu/-/issues/244
** Changed in: qemu
Status: Confirmed => Invalid
** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #244
https://gitlab.com/qemu-project/qemu/-/issues/244
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1926277
Title:
MIPS MT dvpe does not regard VPEConf0.MVP
Status in QEMU:
Invalid
Bug description:
Hi,
According to MIPS32® Architecture for Programmers VolumeIV-f: The
MIPS® MT Application-Specific Extension to the MIPS32® Architecture,
for instruction: dvpe, evpe:
If the VPE executing the instruction is not a Master VPE, with the MVP
bit of the VPEConf0 register set, the EVP bit is unchanged by the
instruction.
The pseudo code is:
data ← MVPControl
GPR[rt] ← data
if(VPEConf0.MVP = 1) then
MVPControl.EVP ← sc
endif
However the helper functions of dvpe, evpe does not regard the
VPEConf0.MVP bit, namely, it does not check if the VPE is a master
VPE. Code is copied below as:
target_ulong helper_dvpe(CPUMIPSState *env)
{
CPUState *other_cs = first_cpu;
target_ulong prev = env->mvp->CP0_MVPControl;
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
/* Turn off all VPEs except the one executing the dvpe. */
if (&other_cpu->env != env) {
other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
}
return prev;
}
Is this a bug?
QEMU head commit: 0cef06d18762374c94eb4d511717a4735d668a24 is checked.
To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1926277/+subscriptions
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-05-09 16:27 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-27 9:19 [Bug 1926277] [NEW] MIPS MT dvpe does not regard VPEConf0.MVP Hansni Bu
2021-04-27 10:35 ` [PATCH] target/mips: Only update MVPControl.EVP bit if executed on a master VPE Philippe Mathieu-Daudé
2021-04-27 10:35 ` [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP Philippe Mathieu-Daudé
2021-04-27 11:42 ` Hansni Bu
2021-04-27 13:29 ` Philippe Mathieu-Daudé
2021-04-27 13:33 ` [PATCH v2] target/mips: Only update MVPControl.EVP bit if executed by master VPE Philippe Mathieu-Daudé
2021-04-27 13:33 ` [Bug 1926277] " Philippe Mathieu-Daudé
2021-05-09 16:16 ` [Bug 1926277] Re: MIPS MT dvpe does not regard VPEConf0.MVP Philippe Mathieu-Daudé
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