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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id z1sm4534730pfg.18.2021.08.12.12.31.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Aug 2021 12:31:35 -0700 (PDT) Subject: Re: [PATCH v2 16/22] target/loongarch: Add floating point move instruction translation To: Song Gao References: <1626861198-6133-1-git-send-email-gaosong@loongson.cn> <1626861198-6133-17-git-send-email-gaosong@loongson.cn> <643a7954-cf1c-78dd-2d08-f0969ea6127e@linaro.org> From: Richard Henderson Message-ID: <1621420e-521d-f12d-230f-6177e3a7cd95@linaro.org> Date: Thu, 12 Aug 2021 09:31:31 -1000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@gmail.com, philmd@redhat.com, yangxiaojuan@loongson.cn, qemu-devel@nongnu.org, maobibo@loongson.cn, laurent@vivier.eu, alistair.francis@wdc.com, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/11/21 11:20 PM, Song Gao wrote: >> This is easily implemented inline, followed by a single helper call to re-load the rounding mode (if required by the mask). > > Hi, Richard, > > Sorry to bother you， When I was revising this patch, I found that I didn't seem to > understand your opinion. Could you explain it in detail? thank you very much. ---%< static const uint32_t fcsr_mask[4] = { UINT32_MAX, FCSR0_M1, FCSR0_M2, FCSR0_M3 }; bool trans_movgr2fcsr(DisasContext *s, arg_movgr2fcsr *a) { uint32_t mask = fcsr_mask[a->fcsr]; if (mask == UINT32_MAX) { tcg_gen_extrl_i64_i32(fpu_fscr0, get_gpr(a->rj)); } else { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(tmp, get_gpr(a->rj)); tcg_gen_andi_i32(tmp, tmp, mask); tcg_gen_andi_i32(fpu_fcsr0, cpu_fcsr0, ~mask); tcg_gen_or_i32(fpu_fcsr0, fpu_fcsr0, tmp); tcg_temp_free_i32(tmp); /* * Install the new rounding mode to fpu_status, if changed. * Note that FCSR3 is exactly the rounding mode field. */ if (mask != FCSR0_M3) { return true; } } gen_helper_set_rounding_mode(cpu_env, fpu_fcsr0); return true; } void trans_movfcsr2gr(DisasContext *s, arg_movfcsr2gr *a) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_andi_i32(tmp, fpu_fcsr0, fcsr_mask[a->fcsr]); tcg_gen_ext_i32_i64(dest_gpr(a->rd), tmp); tcg_temp_free_i32(tmp); return true; } ---%< DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32) ---%< void HELPER(set_rounding_mode)(CPULoongArchState *env, uint32_t fcsr) { set_float_rounding_mode(ieee_rm[(fcsr0 >> FCSR0_RM) & 0x3], &env->fp_status); } r~