From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, qemu-riscv@nongnu.org,
palmer@dabbelt.com, alistair23@gmail.com
Subject: Re: [PATCH 00/38] target/riscv: support packed extension v0.9.2
Date: Tue, 13 Apr 2021 11:27:45 +0800 [thread overview]
Message-ID: <17b7c38a-f780-0216-3e3b-fd0d2178c004@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
ping +1.
On 2021/2/12 下午11:02, LIU Zhiwei wrote:
> This patchset implements the packed extension for RISC-V on QEMU.
>
> This patchset have passed all my direct Linux user mode cases(RV64) and
> bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
> these test cases to my repo(https://github.com/romanheros/qemu.git
> branch:packed-upstream-v1).
>
> I have ported packed extension on RISU, but I didn't find a simulator or
> hardware to compare with. If anyone have one, please let me know.
>
> Features:
> * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
> * support basic packed extension.
> * support Zp64.
>
> LIU Zhiwei (38):
> target/riscv: implementation-defined constant parameters
> target/riscv: Hoist vector functions
> target/riscv: Fixup saturate subtract function
> target/riscv: 16-bit Addition & Subtraction Instructions
> target/riscv: 8-bit Addition & Subtraction Instruction
> target/riscv: SIMD 16-bit Shift Instructions
> target/riscv: SIMD 8-bit Shift Instructions
> target/riscv: SIMD 16-bit Compare Instructions
> target/riscv: SIMD 8-bit Compare Instructions
> target/riscv: SIMD 16-bit Multiply Instructions
> target/riscv: SIMD 8-bit Multiply Instructions
> target/riscv: SIMD 16-bit Miscellaneous Instructions
> target/riscv: SIMD 8-bit Miscellaneous Instructions
> target/riscv: 8-bit Unpacking Instructions
> target/riscv: 16-bit Packing Instructions
> target/riscv: Signed MSW 32x32 Multiply and Add Instructions
> target/riscv: Signed MSW 32x16 Multiply and Add Instructions
> target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
> target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
> target/riscv: Partial-SIMD Miscellaneous Instructions
> target/riscv: 8-bit Multiply with 32-bit Add Instructions
> target/riscv: 64-bit Add/Subtract Instructions
> target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
> target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
> Instructions
> target/riscv: Non-SIMD Q15 saturation ALU Instructions
> target/riscv: Non-SIMD Q31 saturation ALU Instructions
> target/riscv: 32-bit Computation Instructions
> target/riscv: Non-SIMD Miscellaneous Instructions
> target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
> target/riscv: RV64 Only SIMD 32-bit Shift Instructions
> target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
> target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
> target/riscv: RV64 Only 32-bit Multiply Instructions
> target/riscv: RV64 Only 32-bit Multiply & Add Instructions
> target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
> target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
> target/riscv: RV64 Only 32-bit Packing Instructions
> target/riscv: configure and turn on packed extension from command line
>
> target/riscv/cpu.c | 32 +
> target/riscv/cpu.h | 6 +
> target/riscv/helper.h | 332 ++
> target/riscv/insn32-64.decode | 93 +-
> target/riscv/insn32.decode | 285 ++
> target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
> target/riscv/internals.h | 50 +
> target/riscv/meson.build | 1 +
> target/riscv/packed_helper.c | 3862 +++++++++++++++++++++++
> target/riscv/translate.c | 3 +
> target/riscv/vector_helper.c | 90 +-
> 11 files changed, 5912 insertions(+), 66 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
> create mode 100644 target/riscv/packed_helper.c
>
next prev parent reply other threads:[~2021-04-13 3:29 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei [this message]
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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