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Mon, 19 Aug 2019 17:13:37 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7JHDajH47186352 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 19 Aug 2019 17:13:37 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF4386A057; Mon, 19 Aug 2019 17:13:36 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 212386A051; Mon, 19 Aug 2019 17:13:36 +0000 (GMT) Received: from oc3272150783.ibm.com (unknown [9.80.202.43]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Mon, 19 Aug 2019 17:13:35 +0000 (GMT) To: Aleksandar Markovic , David Gibson References: <1565983669-6886-1-git-send-email-pc@us.ibm.com> <0cfddc22-92ef-3067-9275-8f4f22ca9805@linaro.org> <20190819062817.GA24503@umbus.fritz.box> From: Paul Clarke Message-ID: <1b486ed4-512f-e5b3-bcd7-9385b689b1cb@us.ibm.com> Date: Mon, 19 Aug 2019 12:13:34 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-08-19_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908190181 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x7JHB4ob004023 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 148.163.156.1 Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH] ppc: Three floating point fixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 8/19/19 1:44 AM, Aleksandar Markovic wrote: > 19.08.2019. 08.30, "David Gibson" =D1=98=D0= =B5 > =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0=BB=D0=B0: >> >> On Sun, Aug 18, 2019 at 10:59:01PM +0200, Aleksandar Markovic wrote: >>> 18.08.2019. 10.10, "Richard Henderson" = =D1=98=D0=B5 >>> =D0=BD=D0=B0=D0=BF=D0=B8=D1=81=D0=B0=D0=BE/=D0=BB=D0=B0: >>>> >>>> On 8/16/19 11:59 PM, Aleksandar Markovic wrote: >>>>>> From: "Paul A. Clarke" >>>> ... >>>>>> ISA 3.0B has xscvdpspn leaving its result in word 1 of the targe= t >>>>> register, >>>>>> and mffprwz expecting its input to come from word 0 of the sourc= e >>>>> register. >>>>>> This sequence fails with QEMU, as a shift is required between > those >>> two >>>>>> instructions. However, the hardware splats the result to both > word 0 >>>>> and >>>>>> word 1 of its output register, so the shift is not necessary. >>>>>> Expect a future revision of the ISA to specify this behavior. >>>>>> >>>>> >>>>> Hmmm... Isn't this a gcc bug (using undocumented hardware feature), >>> given >>>>> everything you said here? >>>> >>>> The key here is "expect a future revision of the ISA to specify this >>> behavior". >>>> >>>> It's clearly within IBM's purview to adjust the specification to > document >>> a >>>> previously undocumented hardware feature. >>>> >>> >>> By no means, yes, the key is in ISA documentation. But, the impressio= n > that >>> full original commit message conveys is that the main reason for chan= ge > is >>> gcc behavior. If we accepted in general that gcc behavior determines > QEMU >>> behavior, I am afraid we would be on a very slippery slope - therefor= e I >>> think the commit message (and possible code comment) should, in my > opinion, >>> mention ISA docs as the central reason for change. Paul, is there any >>> tentative release date of the new ISA specification? >> >> It's not really a question of gcc behaviour, it's a question of actual >> cpu behaviour versus ISA document. Which one qemu should follow is >> somewhat debatable, but it sounds here like the ISA will be updated to >> match the cpu, which weights it heavily in favour of mimicing the >> actual cpu. >> >=20 > This sounds right to me. Thanks for the reviews and great discussion. While not yet part of a published version of the ISA, I did find the beha= vior documented in the User's Manuals for the POWER8 and POWER9 processor= s: https://www-355.ibm.com/systems/power/openpower/ "Public Documents" - "POWER9 Processor User's Manual" - "POWER8 Processor User's Manual for the SCM" POWER9 Processor User's Manual=20 4. Power Architecture Compliance 4.3 Floating-Point Processor (FP, VMX, and VSX) 4.3.7 Floating-Point Invalid Forms and Undefined Conditions POWER8 Processor User's Manual for the Single-Chip Module 3. Power Architecture Compliance 3.2 Floating-Point Processor (FP, VMX, and VSX) 3.2.9 Floating-Point Invalid Forms and Undefined Conditions In a bullet: - VSX scalar convert from double-precision to single-precision (xscvdpsp,= xscvdpspn). VSR[32:63] is set to VSR[0:31]. I have not confirmed when the new revision of the ISA will be published, = but it's on somebody's "to do" list. I will respin the patch as 3 independent patches, and include a reference= to the above documents for the change under discussion here. (The other= two changes may take a bit more time, because like David, I find the FPU= emulation code cryptic. :-/ ) These issues were found while running Glibc's test suite for "math", and = there are still a *LOT* of QEMU-only FAILs, so I may be back again with s= uggested fixes or questions. :-) PC