From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com,
alistair23@gmail.com
Subject: [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build
Date: Fri, 2 Apr 2021 16:03:07 -0400 [thread overview]
Message-ID: <1c19d0112fae5ec6087cfc415f0d6cc56495220b.1617393702.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1617393702.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn16-32.decode | 24 ++++++++++++++++++++++++
target/riscv/insn16-64.decode | 31 +++++++++++++++++++++++++++++++
target/riscv/translate.c | 18 +++++++++++++++++-
target/riscv/meson.build | 7 +++++--
4 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode
index 0819b17028..f83f43e955 100644
--- a/target/riscv/insn16-32.decode
+++ b/target/riscv/insn16-32.decode
@@ -16,6 +16,30 @@
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
+# Fields imported from insn16.decode:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
+
+# Immediates imported from insn16.decode:
+%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
+%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
+
+# Argument sets imported from insn16.decode:
+&j imm rd !extern
+&i imm rs1 rd !extern
+&s imm rs1 rs2 !extern
+
+# Formats 16 imported from insn16.decode:
+@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
+@cj ... ........... .. &j imm=%imm_cj
+@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
+@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
+@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
+
# *** RV32C Standard Extension (Quadrant 0) ***
flw 011 ... ... .. ... 00 @cl_w
fsw 111 ... ... .. ... 00 @cs_w
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode
index 672e1e916f..dbef1e5365 100644
--- a/target/riscv/insn16-64.decode
+++ b/target/riscv/insn16-64.decode
@@ -16,6 +16,37 @@
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
+# Fields imported from insn16.decode:
+%rd 7:5
+%rs1_3 7:3 !function=ex_rvc_register
+%rs2_3 2:3 !function=ex_rvc_register
+%rs2_5 2:5
+
+# Immediates imported from insn16.decode:
+%imm_ci 12:s1 2:5
+%uimm_cl_d 5:2 10:3 !function=ex_shift_3
+%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
+%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
+
+# Argument sets imported from insn16.decode:
+&empty !extern
+&r rd rs1 rs2 !extern
+&i imm rs1 rd !extern
+&s imm rs1 rs2 !extern
+&j imm rd !extern
+&b imm rs2 rs1 !extern
+&u imm rd !extern
+&shift shamt rs1 rd !extern
+
+# Formats 16 imported from insn16.decode:
+@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
+@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
+@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
+@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
+@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
+@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
+
# *** RV64C Standard Extension (Quadrant 0) ***
ld 011 ... ... .. ... 00 @cl_d
sd 111 ... ... .. ... 00 @cs_d
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4af55deaea..9a93c77fd6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -602,6 +602,10 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
/* Include the auto-generated decoder for 16 bit insn */
#include "decode-insn16.c.inc"
+#include "decode-insn16-32.c.inc"
+#ifdef TARGET_RISCV64
+# include "decode-insn16-64.c.inc"
+#endif
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
{
@@ -612,7 +616,19 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
if (!decode_insn16(ctx, opcode)) {
- gen_exception_illegal(ctx);
+ if (riscv_cpu_is_32bit(env)) {
+ if (!decode_insn16_32(ctx, opcode)) {
+ gen_exception_illegal(ctx);
+ }
+ } else {
+#ifdef TARGET_RISCV64
+ if (!decode_insn16_64(ctx, opcode)) {
+ gen_exception_illegal(ctx);
+ }
+#else
+ gen_exception_illegal(ctx);
+#endif
+ }
}
}
} else {
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 88ab850682..d17b478120 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -1,12 +1,15 @@
# FIXME extra_args should accept files()
dir = meson.current_source_dir()
gen32 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-32.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn16-32.decode', extra_args: ['--static-decode=decode_insn16_32', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'),
]
gen64 = [
- decodetree.process('insn16.decode', extra_args: [dir / 'insn16-64.decode', '--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']),
+ decodetree.process('insn16-32.decode', extra_args: ['--static-decode=decode_insn16_32', '--insnwidth=16']),
+ decodetree.process('insn16-64.decode', extra_args: ['--static-decode=decode_insn16_64', '--insnwidth=16']),
decodetree.process('insn32.decode', extra_args: [dir / 'insn32-64.decode', '--static-decode=decode_insn32']),
]
--
2.31.0
next prev parent reply other threads:[~2021-04-02 20:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 20:02 [PATCH v1 0/8] RISC-V: Steps towards running 32-bit guests on Alistair Francis
2021-04-02 20:02 ` [PATCH v1 1/8] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-04-05 14:48 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 2/8] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-04-05 14:49 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 3/8] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-04-05 14:54 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-04-05 15:10 ` Richard Henderson
2021-04-07 17:11 ` Alistair Francis
2021-04-08 15:20 ` Alistair Francis
2021-04-08 18:51 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 5/8] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-04-05 15:14 ` Richard Henderson
2021-04-02 20:02 ` [PATCH v1 6/8] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:02 ` [PATCH v1 7/8] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-04-05 15:15 ` Richard Henderson
2021-04-12 9:10 ` Bin Meng
2021-04-02 20:03 ` Alistair Francis [this message]
2021-04-06 14:57 ` [PATCH v1 8/8] target/riscv: Include RV32 instructions in RV64 build Richard Henderson
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