Re: [Qemu-devel] [PATCH 6/6] target-ppc: Add helpers for updating a CPU's SDR1 and external HPT

[David Gibson <david@gibson.dropbear.id.au>]

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On Mon, Feb 08, 2016 at 04:11:13PM +1100, Alexey Kardashevskiy wrote:
> On 02/05/2016 01:13 PM, David Gibson wrote:
> >When a Power cpu with 64-bit hash MMU has it's hash page table (HPT)
> >pointer updated by a write to the SDR1 register we need to update some
> >derived variables.  Likewise, when the cpu is configured for an external
> >HPT (one not in the guest memory space) some derived variables need to be
> >updated.
> >
> >Currently the logic for this is (partially) duplicated in ppc_store_sdr1()
> >and in spapr_cpu_reset().  In future we're going to need it in some other
> >places, so make some common helpers for this update.
> >
> >In addition extend the helpers to update SDR1 in KVM - it's not updated
> >by the normal runtime KVM<->qemu CPU synchronization.  Currently there
> >aren't situations where it matters, but there are going to be in future.
> >
> >Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> >---
> >  hw/ppc/spapr.c          | 12 +-----------
> >  target-ppc/kvm.c        | 12 ++++++++++++
> >  target-ppc/kvm_ppc.h    |  6 ++++++
> >  target-ppc/mmu-hash64.c | 36 ++++++++++++++++++++++++++++++++++++
> >  target-ppc/mmu-hash64.h |  4 ++++
> >  target-ppc/mmu_helper.c | 13 ++++++-------
> >  6 files changed, 65 insertions(+), 18 deletions(-)
> >
> >diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> >index 77dd1b6..af3023b 100644
> >--- a/hw/ppc/spapr.c
> >+++ b/hw/ppc/spapr.c
> >@@ -1195,17 +1195,7 @@ static void spapr_cpu_reset(void *opaque)
> >
> >      env->spr[SPR_HIOR] = 0;
> >
> >-    env->external_htab = (uint8_t *)spapr->htab;
> >-    env->htab_base = -1;
> >-    /*
> >-     * htab_mask is the mask used to normalize hash value to PTEG index.
> >-     * htab_shift is log2 of hash table size.
> >-     * We have 8 hpte per group, and each hpte is 16 bytes.
> >-     * ie have 128 bytes per hpte entry.
> >-     */
> >-    env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1;
> >-    env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab |
> >-        (spapr->htab_shift - 18);
> >+    ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift);
> >  }
> >
> >  static void spapr_create_nvram(sPAPRMachineState *spapr)
> >diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
> >index 70ca296..8430d43 100644
> >--- a/target-ppc/kvm.c
> >+++ b/target-ppc/kvm.c
> >@@ -2530,3 +2530,15 @@ int kvmppc_enable_hwrng(void)
> >
> >      return kvmppc_enable_hcall(kvm_state, H_RANDOM);
> >  }
> >+
> >+int kvmppc_update_sdr1(PowerPCCPU *cpu)
> >+{
> >+    CPUState *cs = CPU(cpu);
> >+
> >+    if (!kvm_enabled()) {
> >+        return 0; /* nothing to do */
> >+    }
> >+
> >+    /* This is overkill, but this shouldn't be a common operation */
> >+    return kvm_arch_put_registers(cs, KVM_PUT_RESET_STATE);
> 
> 
> I had to look at kvm_cpu_exec() (which also calls kvm_arch_put_registers) to
> realize that you need here KVM_PUT_RESET_STATE and not kvm_cpu_exec's
> KVM_PUT_RUNTIME_STATE, that should go to the comment imho.

Ok, I'll update that.

> >+}
> >diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
> >index aaa828c..434b3d1 100644
> >--- a/target-ppc/kvm_ppc.h
> >+++ b/target-ppc/kvm_ppc.h
> >@@ -55,6 +55,7 @@ void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index,
> >                               target_ulong pte0, target_ulong pte1);
> >  bool kvmppc_has_cap_fixup_hcalls(void);
> >  int kvmppc_enable_hwrng(void);
> >+int kvmppc_update_sdr1(PowerPCCPU *cpu);
> >
> >  #else
> >
> >@@ -246,6 +247,11 @@ static inline int kvmppc_enable_hwrng(void)
> >  {
> >      return -1;
> >  }
> >+
> >+static inline int kvmppc_update_sdr1(PowerPCCPU *cpu)
> >+{
> >+    return 0; /* nothing to do */
> >+}
> >  #endif
> >
> >  #ifndef CONFIG_KVM
> >diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> >index 9c58fbf..e15d7b0 100644
> >--- a/target-ppc/mmu-hash64.c
> >+++ b/target-ppc/mmu-hash64.c
> >@@ -258,6 +258,42 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
> >  /*
> >   * 64-bit hash table MMU handling
> >   */
> >+void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
> >+                         Error **errp)
> >+{
> >+    CPUPPCState *env = &cpu->env;
> >+    target_ulong htabsize = value & SDR_64_HTABSIZE;
> >+
> >+    cpu_synchronize_state(CPU(cpu));
> >+
> >+    env->spr[SPR_SDR1] = value;
> >+    if (htabsize > 28) {
> >+        error_setg(errp,
> >+                   "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
> >+                   htabsize);
> >+        htabsize = 28;
> >+    }
> >+    env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
> >+    env->htab_base = value & SDR_64_HTABORG;
> >+
> >+    if (kvmppc_update_sdr1(cpu) < 0) {
> >+        error_setg(errp,
> >+                   "Unable to update SDR1 in KVM");
> >+    }
> >+}
> >+
> >+void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift)
> >+{
> >+    CPUPPCState *env = &cpu->env;
> >+
> >+    env->external_htab = hpt;
> >+    ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
> >+                        &error_abort);
> >+
> >+    /* Not strictly necessary, but makes it clearer that an external
> >+     * htab is in use when debugging */
> >+    env->htab_base = -1;
> 
> 
> imho -1 is not really clearer than 0.

It won't be 0 though, because ppc_hash64_set_sdr1() will update it
based on the SDR1 value, which in turn is based on the user address of
the external htab (and PR KVM needs that).
the user address of the external htab.

So, it will look kind of like an address, but won't actually be an
address within the guest AS, which it's supposed to be.  Hence, the
override here.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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