From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWkrL-0007Il-4B for qemu-devel@nongnu.org; Fri, 19 Feb 2016 08:12:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWkrI-0004cM-BV for qemu-devel@nongnu.org; Fri, 19 Feb 2016 08:12:35 -0500 Date: Fri, 19 Feb 2016 14:12:27 +0100 From: "Edgar E. Iglesias" Message-ID: <20160219131227.GB25623@toto> References: <1455287642-28166-1-git-send-email-edgar.iglesias@gmail.com> <1455287642-28166-9-git-send-email-edgar.iglesias@gmail.com> <20160218095654.GD4403@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v1 8/9] target-arm: A64: Create Instruction Syndromes for Data Aborts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Edgar Iglesias , QEMU Developers , qemu-arm , Sergey Fedorov , Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson On Thu, Feb 18, 2016 at 11:42:17AM +0000, Peter Maydell wrote: > On 18 February 2016 at 09:56, Edgar E. Iglesias > wrote: > > On Tue, Feb 16, 2016 at 07:13:32PM +0000, Peter Maydell wrote: > >> I think this patch also would be simpler if the encoded info > >> put in with the TBs was just the syndrome register, rather > >> than some other encoding. > > > > My first try was to only pass the bits needed for the iss > > (i.e not the full data abort syndrome). We don't have all > > the info needed at translation time to create the full > > syndrome (e.g stage2 trap? stage2 trap while stage1 PTW, etc). > > > > But we could maybe create as much of the data abort syndrome > > as possible at translation time and then have the exception > > handling code add the missing bits. We can then pass the > > preliminary syndrome from translation time to exception time > > in the std syndrome format. I can have a look and see what I > > can do if that makes more sense. > > Yep, that was basically what I had in mind. > > Am I right in thinking that at translate time we capture: > IL ISV SAS SSE SRT SF AR > and then at exception time we determine: > EC FnV EA CM S1PTW WnR DFSC > ? Yes. It gets a little messy due to the need to the clearing of ISV (and related fields) and thus setting IL, if the abort does not target EL2 but it's not too bad. > > In that case I think you could reasonably have the info stored > with the TBs be "template syndrome >> 14" (since bits [13:0] are > all info determined at exception-time). The only reason for doing > this is that the encoded data is stored as sleb128 deltas between > lines so keeping the values numerically smaller should make them > take up a bit less space. (I have no idea how significant the > space saving would be.) > > You should then be able to just have restore_state_to_opc() > write straight to env->exception.syndrome rather than needing > a new field in the cpu state. Sounds good! Thanks! Edgar