From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:42796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gkVb2-0002Qc-6y for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gkVb1-000766-Cn for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:12 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36114) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gkVb1-00075M-6Z for qemu-devel@nongnu.org; Fri, 18 Jan 2019 09:58:11 -0500 Received: by mail-wr1-x432.google.com with SMTP id u4so15427439wrp.3 for ; Fri, 18 Jan 2019 06:58:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id e27sm92094561wra.67.2019.01.18.06.58.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 18 Jan 2019 06:58:09 -0800 (PST) From: Peter Maydell Date: Fri, 18 Jan 2019 14:57:18 +0000 Message-Id: <20190118145805.6852-3-peter.maydell@linaro.org> In-Reply-To: <20190118145805.6852-1-peter.maydell@linaro.org> References: <20190118145805.6852-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Eric Auger Let's report IO-coherent access is supported for translation table walks, descriptor fetches and queues by setting the COHACC override flag. Without that, we observe wrong command opcodes. The DT description also advertises the dma coherency. Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table") Signed-off-by: Eric Auger Reported-by: Shameerali Kolothum Thodi Tested-by: Shameer Kolothum Reviewed-by: Andrew Jones Message-id: 20190107101041.765-1-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/acpi/acpi-defs.h | 2 ++ hw/arm/virt-acpi-build.c | 1 + 2 files changed, 3 insertions(+) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 5021cb9e791..df37f687579 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -623,6 +623,8 @@ struct AcpiIortItsGroup { } QEMU_PACKED; typedef struct AcpiIortItsGroup AcpiIortItsGroup; +#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1 + struct AcpiIortSmmu3 { ACPI_IORT_NODE_HEADER_DEF uint64_t base_address; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 95fad6f0ce2..04b62c714d9 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -418,6 +418,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->mapping_count = cpu_to_le32(1); smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); smmu->event_gsiv = cpu_to_le32(irq); smmu->pri_gsiv = cpu_to_le32(irq + 1); smmu->gerr_gsiv = cpu_to_le32(irq + 2); -- 2.20.1