From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Joel Stanley" <joel@jms.id.au>
Subject: [Qemu-devel] [PATCH v2 01/21] aspeed: add a per SoC mapping for the interrupt space
Date: Tue, 18 Jun 2019 18:52:51 +0200 [thread overview]
Message-ID: <20190618165311.27066-2-clg@kaod.org> (raw)
In-Reply-To: <20190618165311.27066-1-clg@kaod.org>
This will simplify the definition of new SoCs, like the AST2600 which
should use a different CPU and a different IRQ number layout.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---
include/hw/arm/aspeed_soc.h | 36 +++++++++++++++++++++++
hw/arm/aspeed_soc.c | 57 +++++++++++++++++++++++++++++++------
2 files changed, 85 insertions(+), 8 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 836b2ba8bf15..963abecb7244 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -56,6 +56,7 @@ typedef struct AspeedSoCInfo {
const char *fmc_typename;
const char **spi_typename;
int wdts_num;
+ const int *irqmap;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {
@@ -68,4 +69,39 @@ typedef struct AspeedSoCClass {
#define ASPEED_SOC_GET_CLASS(obj) \
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
+enum {
+ ASPEED_IOMEM,
+ ASPEED_UART1,
+ ASPEED_UART2,
+ ASPEED_UART3,
+ ASPEED_UART4,
+ ASPEED_UART5,
+ ASPEED_VUART,
+ ASPEED_FMC,
+ ASPEED_SPI1,
+ ASPEED_SPI2,
+ ASPEED_VIC,
+ ASPEED_SDMC,
+ ASPEED_SCU,
+ ASPEED_ADC,
+ ASPEED_SRAM,
+ ASPEED_GPIO,
+ ASPEED_RTC,
+ ASPEED_TIMER1,
+ ASPEED_TIMER2,
+ ASPEED_TIMER3,
+ ASPEED_TIMER4,
+ ASPEED_TIMER5,
+ ASPEED_TIMER6,
+ ASPEED_TIMER7,
+ ASPEED_TIMER8,
+ ASPEED_WDT,
+ ASPEED_PWM,
+ ASPEED_LPC,
+ ASPEED_IBT,
+ ASPEED_I2C,
+ ASPEED_ETH1,
+ ASPEED_ETH2,
+};
+
#endif /* ASPEED_SOC_H */
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index a2ea8c748449..de75bf04027d 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -38,12 +38,42 @@
#define ASPEED_SOC_ETH1_BASE 0x1E660000
#define ASPEED_SOC_ETH2_BASE 0x1E680000
-static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
-static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
+static const int aspeed_soc_ast2400_irqmap[] = {
+ [ASPEED_UART1] = 9,
+ [ASPEED_UART2] = 32,
+ [ASPEED_UART3] = 33,
+ [ASPEED_UART4] = 34,
+ [ASPEED_UART5] = 10,
+ [ASPEED_VUART] = 8,
+ [ASPEED_FMC] = 19,
+ [ASPEED_SDMC] = 0,
+ [ASPEED_SCU] = 21,
+ [ASPEED_ADC] = 31,
+ [ASPEED_GPIO] = 20,
+ [ASPEED_RTC] = 22,
+ [ASPEED_TIMER1] = 16,
+ [ASPEED_TIMER2] = 17,
+ [ASPEED_TIMER3] = 18,
+ [ASPEED_TIMER4] = 35,
+ [ASPEED_TIMER5] = 36,
+ [ASPEED_TIMER6] = 37,
+ [ASPEED_TIMER7] = 38,
+ [ASPEED_TIMER8] = 39,
+ [ASPEED_WDT] = 27,
+ [ASPEED_PWM] = 28,
+ [ASPEED_LPC] = 8,
+ [ASPEED_IBT] = 8, /* LPC */
+ [ASPEED_I2C] = 12,
+ [ASPEED_ETH1] = 2,
+ [ASPEED_ETH2] = 3,
+};
#define AST2400_SDRAM_BASE 0x40000000
#define AST2500_SDRAM_BASE 0x80000000
+/* AST2500 uses the same IRQs as the AST2400 */
+#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
+
static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
@@ -64,6 +94,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
.wdts_num = 2,
+ .irqmap = aspeed_soc_ast2400_irqmap,
}, {
.name = "ast2400-a1",
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
@@ -75,6 +106,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
.wdts_num = 2,
+ .irqmap = aspeed_soc_ast2400_irqmap,
}, {
.name = "ast2400",
.cpu_type = ARM_CPU_TYPE_NAME("arm926"),
@@ -86,6 +118,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
.wdts_num = 2,
+ .irqmap = aspeed_soc_ast2400_irqmap,
}, {
.name = "ast2500-a1",
.cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
@@ -97,9 +130,17 @@ static const AspeedSoCInfo aspeed_socs[] = {
.fmc_typename = "aspeed.smc.ast2500-fmc",
.spi_typename = aspeed_soc_ast2500_typenames,
.wdts_num = 3,
+ .irqmap = aspeed_soc_ast2500_irqmap,
},
};
+static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
+}
+
static void aspeed_soc_init(Object *obj)
{
AspeedSoCState *s = ASPEED_SOC(obj);
@@ -216,14 +257,14 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
- for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
- qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
+ for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
+ qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hd(0)) {
- qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
+ qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
serial_mm_init(get_system_memory(),
ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2,
uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
@@ -237,7 +278,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
- qdev_get_gpio_in(DEVICE(&s->vic), 12));
+ aspeed_soc_get_irq(s, ASPEED_I2C));
/* FMC, The number of CS is set at the board level */
object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
@@ -249,7 +290,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
s->fmc.ctrl->flash_window_base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
- qdev_get_gpio_in(DEVICE(&s->vic), 19));
+ aspeed_soc_get_irq(s, ASPEED_FMC));
/* SPI */
for (i = 0; i < sc->info->spis_num; i++) {
@@ -297,7 +338,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
- qdev_get_gpio_in(DEVICE(&s->vic), 2));
+ aspeed_soc_get_irq(s, ASPEED_ETH1));
}
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
--
2.21.0
next prev parent reply other threads:[~2019-06-18 17:11 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 16:52 [Qemu-devel] [PATCH v2 00/21] aspeed: machine extensions and fixes Cédric Le Goater
2019-06-18 16:52 ` Cédric Le Goater [this message]
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 02/21] aspeed: add a per SoC mapping for the memory space Cédric Le Goater
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 03/21] hw: timer: Add ASPEED RTC device Cédric Le Goater
2019-07-02 19:19 ` Peter Maydell
2019-07-04 7:49 ` Joel Stanley
2019-07-04 13:08 ` Peter Maydell
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 04/21] hw/arm/aspeed: Add RTC to SoC Cédric Le Goater
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 05/21] aspeed: introduce a configurable number of CPU per machine Cédric Le Goater
2019-06-19 2:10 ` Joel Stanley
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 06/21] aspeed: add support for multiple NICs Cédric Le Goater
2019-06-19 2:11 ` Joel Stanley
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 07/21] aspeed/timer: Fix behaviour running Linux Cédric Le Goater
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 08/21] aspeed/timer: Status register contains reload for stopped timer Cédric Le Goater
2019-06-19 2:12 ` Joel Stanley
2019-06-18 16:52 ` [Qemu-devel] [PATCH v2 09/21] aspeed/timer: Fix match calculations Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 10/21] aspeed/timer: Provide back-pressure information for short periods Cédric Le Goater
2019-07-01 12:59 ` Peter Maydell
2019-07-01 13:38 ` Cédric Le Goater
2019-07-03 8:53 ` Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 11/21] aspeed/timer: Ensure positive muldiv delta Cédric Le Goater
2019-06-19 2:15 ` Joel Stanley
2019-06-20 2:05 ` Andrew Jeffery
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 12/21] aspeed: remove the "ram" link Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 13/21] aspeed: add a RAM memory region container Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 14/21] aspeed/smc: add a 'sdram_base' property Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 15/21] aspeed/smc: add support for DMAs Cédric Le Goater
2019-07-01 13:06 ` Peter Maydell
2019-07-01 13:50 ` Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 16/21] aspeed/smc: add DMA calibration settings Cédric Le Goater
2019-07-01 13:19 ` Peter Maydell
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 17/21] aspeed/smc: inject errors in DMA checksum Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 18/21] aspeed/smc: Calculate checksum on normal DMA Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 19/21] aspeed: Add support for the swift-bmc board Cédric Le Goater
2019-06-19 2:24 ` Joel Stanley
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 20/21] hw/misc/aspeed_xdma: New device Cédric Le Goater
2019-06-18 16:53 ` [Qemu-devel] [PATCH v2 21/21] aspeed: vic: Add support for legacy register interface Cédric Le Goater
2019-06-19 2:08 ` Joel Stanley
2019-07-01 13:35 ` [Qemu-devel] [PATCH v2 00/21] aspeed: machine extensions and fixes Peter Maydell
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