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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-devel] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding
Date: Wed,  3 Jul 2019 01:40:27 -0700	[thread overview]
Message-ID: <20190703084048.6980-12-palmer@sifive.com> (raw)
In-Reply-To: <20190703084048.6980-1-palmer@sifive.com>

From: Bin Meng <bmeng.cn@gmail.com>

The largest pci bus number should be calculated from ECAM size,
instead of its base address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..487f61404b21 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -298,7 +298,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
-                           memmap[VIRT_PCIE_ECAM].base /
+                           memmap[VIRT_PCIE_ECAM].size /
                                PCIE_MMCFG_SIZE_MIN - 1);
     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
-- 
2.21.0



  parent reply	other threads:[~2019-07-03  8:51 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-03  8:40 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 02/32] sifive_prci: Read and write PRCI registers Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 03/32] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt
2019-08-01 15:39   ` Peter Maydell
2019-08-13 22:44     ` Palmer Dabbelt
2019-08-15 21:39       ` Alistair Francis
2019-08-15 22:17         ` Palmer Dabbelt
2019-08-16  8:57           ` Peter Maydell
2019-09-17 13:56             ` Peter Maydell
2019-09-17 16:37               ` Alistair Francis
2019-09-20 22:40                 ` Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 08/32] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt
2019-07-03  8:40 ` Palmer Dabbelt [this message]
2019-07-03  8:40 ` [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 13/32] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 15/32] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 18/32] target/riscv: Require either I or E base extension Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 19/32] target/riscv: Remove user version information Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 21/32] RISC-V: Add support for the Zifencei extension Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 22/32] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 24/32] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 25/32] riscv: virt: Add cpu-topology DT node Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 30/32] hw/riscv: Split out the boot functions Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 31/32] hw/riscv: Add support for loading a firmware Palmer Dabbelt
2019-07-03  8:40 ` [Qemu-devel] [PULL 32/32] hw/riscv: Extend the kernel loading support Palmer Dabbelt
2019-07-04 10:40 ` [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3 Peter Maydell

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