From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2100C5B578 for ; Wed, 3 Jul 2019 08:54:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CF819218A3 for ; Wed, 3 Jul 2019 08:54:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CF819218A3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:33792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hib22-0002Sy-4n for qemu-devel@archiver.kernel.org; Wed, 03 Jul 2019 04:54:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51385) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hiapb-00064H-RU for qemu-devel@nongnu.org; Wed, 03 Jul 2019 04:41:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hiapa-0006xm-Ce for qemu-devel@nongnu.org; Wed, 03 Jul 2019 04:41:35 -0400 Received: from mail-lf1-f44.google.com ([209.85.167.44]:34606) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hiapa-0006sW-32 for qemu-devel@nongnu.org; Wed, 03 Jul 2019 04:41:34 -0400 Received: by mail-lf1-f44.google.com with SMTP id b29so1181868lfq.1 for ; Wed, 03 Jul 2019 01:41:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=4yIbg4wQD3g4mppuKoX6VmO7ZtWwJtsrHDtVUEb9gdk=; b=h53bureD0E5Njc77Vf0CxOtIjGO7pi/VgrkB6DeDFLwQmU0RjeWdkUUckGTFsUVYyU DkNh3xM4xg0Hj40MG2sZrBRVmDhGTQVsyhiOfNCXM4IRo0Xp5ExaM3/yUl3/YwvIThEu kwfCtXZmO8lhUeysVPsAQybvF6yd/+9lDR/JMWZbvzqJl+T2KGxLCTq5rl44EwjWT9Ms aoGglNkjub8mdJXb6Ghdxh8kv9lhvyFhy8yv6xqg0TN+QhrvwWr1+xga30+EWkD2I0Sd xdtQKR7miPAXMk8MdxsYYrYnfli2zHmwCSZR6YxfW22WXtmOEynTyvUZ7LND09bXJWsd ytDA== X-Gm-Message-State: APjAAAWZEerZsWJwvNC3MvFYO00nqnI0G9eZeygNSDy9kvZv1GmPPgza fNKJC3gBnLxTnYD3SdLjXU1okn3SbzkHwQ== X-Google-Smtp-Source: APXvYqzUL7DCZEzl/s+Kdth5aRdGBT/V7Hmgise26dm3QFGlUj3Q8nbrEh/Gytj/tVhVEJDPpf2UMg== X-Received: by 2002:a19:ec15:: with SMTP id b21mr18835270lfa.32.1562143291306; Wed, 03 Jul 2019 01:41:31 -0700 (PDT) Received: from localhost ([134.17.27.127]) by smtp.gmail.com with ESMTPSA id a17sm286737lfg.73.2019.07.03.01.41.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 03 Jul 2019 01:41:30 -0700 (PDT) Date: Wed, 3 Jul 2019 01:40:28 -0700 Message-Id: <20190703084048.6980-13-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190703084048.6980-1-palmer@sifive.com> References: <20190703084048.6980-1-palmer@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.167.44 Subject: [Qemu-devel] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(), where a pair of recently added MemoryRegion instances would not be freed if there were errors elsewhere in the function. The fix here is to simply not use dynamic allocation for these instances: there's always one of each in SiFiveESoCState, so instead we just include them within the struct. Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device") Signed-off-by: Palmer Dabbelt Suggested-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/riscv/sifive_e.c | 13 ++++++------- include/hw/riscv/sifive_e.h | 2 ++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 80ac56fa7d5e..a5b4086da36d 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -158,17 +158,15 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); - MemoryRegion *xip_mem = g_new(MemoryRegion, 1); - MemoryRegion *mask_rom = g_new(MemoryRegion, 1); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); /* Mask ROM */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.e.mrom", + memory_region_init_rom(&s->mask_rom, NULL, "riscv.sifive.e.mrom", memmap[SIFIVE_E_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, mask_rom); + memmap[SIFIVE_E_MROM].base, &s->mask_rom); /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, @@ -228,10 +226,11 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); /* Flash memory */ - memory_region_init_ram(xip_mem, NULL, "riscv.sifive.e.xip", + memory_region_init_ram(&s->xip_mem, NULL, "riscv.sifive.e.xip", memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_set_readonly(xip_mem, true); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, xip_mem); + memory_region_set_readonly(&s->xip_mem, true); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, + &s->xip_mem); } static void riscv_sifive_e_machine_init(MachineClass *mc) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 3b14eb74621f..d175b24cb209 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -33,6 +33,8 @@ typedef struct SiFiveESoCState { RISCVHartArrayState cpus; DeviceState *plic; SIFIVEGPIOState gpio; + MemoryRegion xip_mem; + MemoryRegion mask_rom; } SiFiveESoCState; typedef struct SiFiveEState { -- 2.21.0