From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate
Date: Fri, 26 Jul 2019 10:49:41 -0700 [thread overview]
Message-ID: <20190726175032.6769-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 216 ++++++++++++++++++++++-------------------
target/arm/a32.decode | 20 ++++
target/arm/t32.decode | 29 ++++++
3 files changed, 167 insertions(+), 98 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 85f829c1bb..2140671eb2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8216,6 +8216,114 @@ DO_QADDSUB(QDSUB, false, true)
#undef DO_QADDSUB
+/*
+ * Halfword multiply and multiply accumulate
+ */
+
+static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
+ int add_long, bool nt, bool mt)
+{
+ TCGv_i32 t0, t1, tl, th;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ gen_mulxy(t0, t1, nt, mt);
+ tcg_temp_free_i32(t1);
+
+ switch (add_long) {
+ case 0:
+ store_reg(s, a->rd, t0);
+ break;
+ case 1:
+ t1 = load_reg(s, a->ra);
+ gen_helper_add_setq(t0, cpu_env, t0, t1);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ break;
+ case 2:
+ tl = load_reg(s, a->ra);
+ th = load_reg(s, a->rd);
+ tcg_gen_add2_i32(tl, th, tl, th, t0, t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->ra, tl);
+ store_reg(s, a->rd, th);
+ }
+ return true;
+}
+
+#define DO_SMLAX(NAME, add, nt, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlaxxx(s, a, add, nt, mt); \
+}
+
+DO_SMLAX(SMULBB, 0, 0, 0)
+DO_SMLAX(SMULBT, 0, 0, 1)
+DO_SMLAX(SMULTB, 0, 1, 0)
+DO_SMLAX(SMULTT, 0, 1, 1)
+
+DO_SMLAX(SMLABB, 1, 0, 0)
+DO_SMLAX(SMLABT, 1, 0, 1)
+DO_SMLAX(SMLATB, 1, 1, 0)
+DO_SMLAX(SMLATT, 1, 1, 1)
+
+DO_SMLAX(SMLALBB, 2, 0, 0)
+DO_SMLAX(SMLALBT, 2, 0, 1)
+DO_SMLAX(SMLALTB, 2, 1, 0)
+DO_SMLAX(SMLALTT, 2, 1, 1)
+
+#undef DO_SMLAX
+
+static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
+{
+ TCGv_i32 t0, t1;
+
+ if (!ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ /*
+ * Since the nominal result is product<47:16>, shift the 16-bit
+ * input up by 16 bits, so that the result is at product<63:32>.
+ */
+ if (mt) {
+ tcg_gen_andi_i32(t1, t1, 0xffff0000);
+ } else {
+ tcg_gen_shli_i32(t1, t1, 16);
+ }
+ tcg_gen_muls2_i32(t0, t1, t0, t1);
+ tcg_temp_free_i32(t0);
+ if (add) {
+ t0 = load_reg(s, a->ra);
+ gen_helper_add_setq(t1, cpu_env, t1, t0);
+ tcg_temp_free_i32(t0);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+#define DO_SMLAWX(NAME, add, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlawx(s, a, add, mt); \
+}
+
+DO_SMLAWX(SMULWB, 0, 0)
+DO_SMLAWX(SMULWT, 0, 1)
+DO_SMLAWX(SMLAWB, 1, 0)
+DO_SMLAWX(SMLAWT, 1, 1)
+
+#undef DO_SMLAWX
+
/*
* Legacy decoder.
*/
@@ -8680,56 +8788,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
break;
}
- case 0x8: /* signed multiply */
+ case 0x8:
case 0xa:
case 0xc:
case 0xe:
- ARCH(5TE);
- rs = (insn >> 8) & 0xf;
- rn = (insn >> 12) & 0xf;
- rd = (insn >> 16) & 0xf;
- if (op1 == 1) {
- /* (32 * 16) >> 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- if (sh & 4)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if ((sh & 2) == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- } else {
- /* 16 * 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
- tcg_temp_free_i32(tmp2);
- if (op1 == 2) {
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
- gen_addq(s, tmp64, rn, rd);
- gen_storeq_reg(s, rn, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- } else {
- if (op1 == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- }
- }
- break;
+ /* Halfword multiply and multiply accumulate. */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
default:
goto illegal_op;
}
@@ -10189,11 +10254,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
switch ((insn >> 20) & 7) {
case 0: /* 32 x 32 -> 32 */
+ case 1: /* 16 x 16 -> 32 */
+ case 3: /* 32 * 16 -> 32msb */
+ /* in decodetree */
+ goto illegal_op;
case 7: /* Unsigned sum of absolute differences. */
break;
- case 1: /* 16 x 16 -> 32 */
case 2: /* Dual multiply add. */
- case 3: /* 32 * 16 -> 32msb */
case 4: /* Dual multiply subtract. */
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
@@ -10205,27 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
switch ((insn >> 20) & 7) {
- case 0: /* 32 x 32 -> 32 */
- tcg_gen_mul_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- if (op)
- tcg_gen_sub_i32(tmp, tmp2, tmp);
- else
- tcg_gen_add_i32(tmp, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
- case 1: /* 16 x 16 -> 32 */
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 2: /* Dual multiply add. */
case 4: /* Dual multiply subtract. */
if (op)
@@ -10249,23 +10295,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp2);
}
break;
- case 3: /* 32 * 16 -> 32msb */
- if (op)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
tmp64 = gen_muls_i64_i32(tmp, tmp2);
if (rs != 15) {
@@ -10340,17 +10369,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp64 = gen_mulu_i64_i32(tmp, tmp2);
} else {
if (op & 8) {
- /* smlalxy */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- goto illegal_op;
- }
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
- tcg_temp_free_i32(tmp2);
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
+ /* smlalxy, in decodetree */
+ goto illegal_op;
} else {
/* Signed 64-bit multiply */
tmp64 = gen_muls_i64_i32(tmp, tmp2);
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index af6712a9e8..8dc74dfdb8 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -114,6 +114,7 @@ MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot
@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
+@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0
MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
@@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm
QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm
QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm
QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm
+
+# Halfword multiply and multiply accumulate
+
+SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn
+SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn
+SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn
+SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn
+SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn
+SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn
+SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn
+SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn
+SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn
+SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn
+SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn
+SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn
+SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn
+SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn
+SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn
+SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 7a27b5cc5c..e611ac4969 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
+@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
{
@@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
+{
+ SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm
+ SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm
+ SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm
+ SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm
+ SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm
+ SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm
+}
+{
+ SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm
+ SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm
+}
+SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm
+SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm
+SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm
+SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
# Data-processing (two source registers)
--
2.17.1
next prev parent reply other threads:[~2019-07-26 17:55 UTC|newest]
Thread overview: 110+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 17:49 [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits Richard Henderson
2019-07-29 13:43 ` Peter Maydell
2019-07-30 1:30 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn Richard Henderson
2019-07-29 13:48 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn Richard Henderson
2019-07-29 13:50 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn Richard Henderson
2019-07-29 13:52 ` Peter Maydell
2019-07-30 2:11 ` Richard Henderson
2019-08-06 9:55 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address Richard Henderson
2019-07-29 13:54 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read Richard Henderson
2019-07-29 14:05 ` Peter Maydell
2019-07-30 0:38 ` Richard Henderson
2019-08-06 10:00 ` Peter Maydell
2019-08-06 15:04 ` Richard Henderson
2019-08-06 15:21 ` Peter Maydell
2019-08-06 15:53 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit Richard Henderson
2019-07-29 14:15 ` Peter Maydell
2019-07-30 0:51 ` Richard Henderson
2019-08-06 9:44 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-07-29 14:26 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg Richard Henderson
2019-07-29 14:27 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless Richard Henderson
2019-07-29 14:32 ` Peter Maydell
2019-07-30 0:57 ` Richard Henderson
2019-07-30 8:49 ` Peter Maydell
2019-07-26 17:49 ` [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-07-29 14:42 ` Peter Maydell
2019-08-06 21:41 ` Philippe Mathieu-Daudé
2019-08-08 11:41 ` Aleksandar Markovic
2019-08-08 15:43 ` Richard Henderson
2019-08-09 10:31 ` Aleksandar Markovic
2019-08-09 14:55 ` Richard Henderson
2019-08-09 15:30 ` Aleksandar Markovic
2019-07-26 17:49 ` [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op Richard Henderson
2019-07-29 14:44 ` Peter Maydell
2019-08-06 21:43 ` Philippe Mathieu-Daudé
2019-07-26 17:49 ` [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) Richard Henderson
2019-07-29 15:25 ` Peter Maydell
2019-07-30 1:25 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-05 15:32 ` Peter Maydell
2019-08-05 16:20 ` Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-05 15:40 ` Peter Maydell
2019-07-26 17:49 ` Richard Henderson [this message]
2019-07-26 17:49 ` [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-07-26 17:49 ` [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 39/67] target/arm: Convert SG Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 40/67] target/arm: Convert TT Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb Richard Henderson
2019-07-26 18:13 ` Peter Maydell
2019-07-26 18:34 ` Richard Henderson
2019-07-26 17:50 ` [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i Richard Henderson
2019-07-26 18:40 ` [Qemu-devel] [PATCH 00/67] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-05 15:44 ` Peter Maydell
2019-08-05 21:26 ` Richard Henderson
2019-08-06 10:01 ` Peter Maydell
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