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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn
Date: Fri, 16 Aug 2019 14:17:04 +0100
Message-ID: <20190816131719.28244-15-peter.maydell@linaro.org> (raw)
In-Reply-To: <20190816131719.28244-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Unlike the other more generic gen_exception{,_internal}_insn
interfaces, breakpoints always refer to the current instruction.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190807045335.1361-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 7 +++----
 target/arm/translate.c     | 8 ++++----
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2f8eea02e3b..55324333dab 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -268,12 +268,11 @@ static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception_bkpt_insn(DisasContext *s, int offset,
-                                    uint32_t syndrome)
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
 {
     TCGv_i32 tcg_syn;
 
-    gen_a64_set_pc_im(s->base.pc_next - offset);
+    gen_a64_set_pc_im(s->pc_curr);
     tcg_syn = tcg_const_i32(syndrome);
     gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
     tcg_temp_free_i32(tcg_syn);
@@ -1900,7 +1899,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
             break;
         }
         /* BRK */
-        gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16));
+        gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
         break;
     case 2:
         if (op2_ll != 0) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c26d3376b3c..8bae0c39933 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1258,12 +1258,12 @@ static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 {
     TCGv_i32 tcg_syn;
 
     gen_set_condexec(s);
-    gen_set_pc_im(s, s->base.pc_next - offset);
+    gen_set_pc_im(s, s->pc_curr);
     tcg_syn = tcg_const_i32(syn);
     gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
     tcg_temp_free_i32(tcg_syn);
@@ -8140,7 +8140,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             case 1:
                 /* bkpt */
                 ARCH(5);
-                gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
+                gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
                 break;
             case 2:
                 /* Hypervisor call (v7) */
@@ -11566,7 +11566,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
         {
             int imm8 = extract32(insn, 0, 8);
             ARCH(5);
-            gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
+            gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
             break;
         }
 
-- 
2.20.1



  parent reply index

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16 13:16 [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc Peter Maydell
2019-08-16 13:16 ` [Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1 Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn Peter Maydell
2019-08-16 13:17 ` Peter Maydell [this message]
2019-08-16 13:17 ` [Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32 Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR Peter Maydell
2019-08-16 13:17 ` [Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word Peter Maydell
2019-08-16 17:02 ` [Qemu-devel] [PULL 00/29] target-arm queue Peter Maydell

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