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From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Yoshinori Sato" <ysato@users.sourceforge.jp>,
	imammedo@redhat.com
Subject: [Qemu-devel] [PATCH v23 03/22] hw/registerfields.h: Add 8bit and 16bit register macros
Date: Sat, 17 Aug 2019 16:36:09 +0900
Message-ID: <20190817073628.94473-4-ysato@users.sourceforge.jp> (raw)
In-Reply-To: <20190817073628.94473-1-ysato@users.sourceforge.jp>

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190607091116.49044-11-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..a0bb0654d6 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
     enum { A_ ## reg = (addr) };                                          \
     enum { R_ ## reg = (addr) / 4 };
 
+#define REG8(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) / 2 };
+
 /* Define SHIFT, LENGTH and MASK constants for a field within a register */
 
 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
                                         MAKE_64BIT_MASK(shift, length)};
 
 /* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field)                                    \
+    extract8((storage), R_ ## reg ## _ ## field ## _SHIFT,                \
+              R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field)                                   \
+    extract16((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
+              R_ ## reg ## _ ## field ## _LENGTH)
 #define FIELD_EX32(storage, reg, field)                                   \
     extract32((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
               R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
  * Assigning values larger then the target field will result in
  * compilation warnings.
  */
+#define FIELD_DP8(storage, reg, field, val) ({                            \
+    struct {                                                              \
+        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+    } v = { .v = val };                                                   \
+    uint8_t d;                                                            \
+    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
+                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
+    d; })
+#define FIELD_DP16(storage, reg, field, val) ({                           \
+    struct {                                                              \
+        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+    } v = { .v = val };                                                   \
+    uint16_t d;                                                           \
+    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
+                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
+    d; })
 #define FIELD_DP32(storage, reg, field, val) ({                           \
     struct {                                                              \
         unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
@@ -57,7 +87,7 @@
     d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
                   R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
     d; })
-#define FIELD_DP64(storage, reg, field, val) ({                           \
+#define FIELD_DP64(storage, reg, field, val) ({                         \
     struct {                                                              \
         unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
     } v = { .v = val };                                                   \
-- 
2.11.0



  parent reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-17  7:36 [Qemu-devel] [PATCH v23 00/22] Add RX archtecture support Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 01/22] MAINTAINERS: Add RX Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 02/22] qemu/bitops.h: Add extract8 and extract16 Yoshinori Sato
2019-08-17  7:36 ` Yoshinori Sato [this message]
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 04/22] target/rx: TCG translation Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 05/22] target/rx: TCG helper Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 06/22] target/rx: CPU definition Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 07/22] target/rx: RX disassembler Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 08/22] target/rx: Disassemble rx_index_addr into a string Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 09/22] target/rx: Replace operand with prt_ldmi in disassembler Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 10/22] target/rx: Use prt_ldmi for XCHG_mr disassembly Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 11/22] target/rx: Emit all disassembly in one prt() Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 12/22] target/rx: Collect all bytes during disassembly Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 13/22] target/rx: Dump bytes for each insn " Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 14/22] hw/intc: RX62N interrupt controller (ICUa) Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 15/22] hw/timer: RX62N internal timer modules Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 16/22] hw/char: RX62N serial communication interface (SCI) Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 17/22] hw/rx: RX Target hardware definition Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 18/22] hw/rx: Honor -accel qtest Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 19/22] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 20/22] Add rx-softmmu Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 21/22] BootLinuxConsoleTest: Test the RX-Virt machine Yoshinori Sato
2019-08-17  7:36 ` [Qemu-devel] [PATCH v23 22/22] target/rx: remove unused functions Yoshinori Sato
2019-08-21 10:23   ` Philippe Mathieu-Daudé
2019-08-21 14:33     ` Yoshinori Sato
2019-08-17  8:07 ` [Qemu-devel] [PATCH v23 00/22] Add RX archtecture support no-reply
2019-08-17  8:22 ` no-reply
2019-08-17  8:37 ` no-reply
2019-08-17  8:53 ` no-reply
2019-08-17  9:09 ` no-reply
2019-08-17  9:23 ` no-reply
2019-08-17  9:39 ` no-reply
2019-08-17  9:48 ` no-reply
2019-08-21  9:28 ` Yoshinori Sato
2019-08-21 10:28 ` Philippe Mathieu-Daudé
2019-09-02 15:02   ` Philippe Mathieu-Daudé

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