From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate
Date: Mon, 19 Aug 2019 14:36:56 -0700 [thread overview]
Message-ID: <20190819213755.26175-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 218 +++++++++++++++++++++++------------------
target/arm/a32.decode | 20 ++++
target/arm/t32.decode | 29 ++++++
3 files changed, 170 insertions(+), 97 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b731e08fe4..56ae83a7d0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8141,6 +8141,117 @@ DO_QADDSUB(QDSUB, false, true)
#undef DO_QADDSUB
+/*
+ * Halfword multiply and multiply accumulate
+ */
+
+static bool op_smlaxxx(DisasContext *s, arg_rrrr *a,
+ int add_long, bool nt, bool mt)
+{
+ TCGv_i32 t0, t1;
+ TCGv_i64 t64;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ gen_mulxy(t0, t1, nt, mt);
+ tcg_temp_free_i32(t1);
+
+ switch (add_long) {
+ case 0:
+ store_reg(s, a->rd, t0);
+ break;
+ case 1:
+ t1 = load_reg(s, a->ra);
+ gen_helper_add_setq(t0, cpu_env, t0, t1);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ break;
+ case 2:
+ t64 = tcg_temp_new_i64();
+ tcg_gen_ext_i32_i64(t64, t0);
+ tcg_temp_free_i32(t0);
+ gen_addq(s, t64, a->ra, a->rd);
+ gen_storeq_reg(s, a->ra, a->rd, t64);
+ tcg_temp_free_i64(t64);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+#define DO_SMLAX(NAME, add, nt, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlaxxx(s, a, add, nt, mt); \
+}
+
+DO_SMLAX(SMULBB, 0, 0, 0)
+DO_SMLAX(SMULBT, 0, 0, 1)
+DO_SMLAX(SMULTB, 0, 1, 0)
+DO_SMLAX(SMULTT, 0, 1, 1)
+
+DO_SMLAX(SMLABB, 1, 0, 0)
+DO_SMLAX(SMLABT, 1, 0, 1)
+DO_SMLAX(SMLATB, 1, 1, 0)
+DO_SMLAX(SMLATT, 1, 1, 1)
+
+DO_SMLAX(SMLALBB, 2, 0, 0)
+DO_SMLAX(SMLALBT, 2, 0, 1)
+DO_SMLAX(SMLALTB, 2, 1, 0)
+DO_SMLAX(SMLALTT, 2, 1, 1)
+
+#undef DO_SMLAX
+
+static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt)
+{
+ TCGv_i32 t0, t1;
+ TCGv_i64 t64;
+
+ if (!ENABLE_ARCH_5TE) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+ if (mt) {
+ tcg_gen_sari_i32(t1, t1, 16);
+ } else {
+ gen_sxth(t1);
+ }
+ t64 = gen_muls_i64_i32(t0, t1);
+ tcg_gen_shri_i64(t64, t64, 16);
+ t1 = tcg_temp_new_i32();
+ tcg_gen_extrl_i64_i32(t1, t64);
+ tcg_temp_free_i64(t64);
+ if (add) {
+ t0 = load_reg(s, a->ra);
+ gen_helper_add_setq(t1, cpu_env, t1, t0);
+ tcg_temp_free_i32(t0);
+ }
+ store_reg(s, a->rd, t1);
+ return true;
+}
+
+#define DO_SMLAWX(NAME, add, mt) \
+static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \
+{ \
+ return op_smlawx(s, a, add, mt); \
+}
+
+DO_SMLAWX(SMULWB, 0, 0)
+DO_SMLAWX(SMULWT, 0, 1)
+DO_SMLAWX(SMLAWB, 1, 0)
+DO_SMLAWX(SMLAWT, 1, 1)
+
+#undef DO_SMLAWX
+
/*
* Legacy decoder.
*/
@@ -8607,56 +8718,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
break;
}
- case 0x8: /* signed multiply */
+ case 0x8:
case 0xa:
case 0xc:
case 0xe:
- ARCH(5TE);
- rs = (insn >> 8) & 0xf;
- rn = (insn >> 12) & 0xf;
- rd = (insn >> 16) & 0xf;
- if (op1 == 1) {
- /* (32 * 16) >> 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- if (sh & 4)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if ((sh & 2) == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- } else {
- /* 16 * 16 */
- tmp = load_reg(s, rm);
- tmp2 = load_reg(s, rs);
- gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
- tcg_temp_free_i32(tmp2);
- if (op1 == 2) {
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
- tcg_temp_free_i32(tmp);
- gen_addq(s, tmp64, rn, rd);
- gen_storeq_reg(s, rn, rd, tmp64);
- tcg_temp_free_i64(tmp64);
- } else {
- if (op1 == 0) {
- tmp2 = load_reg(s, rn);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- store_reg(s, rd, tmp);
- }
- }
- break;
+ /* Halfword multiply and multiply accumulate. */
+ /* All done in decodetree. Reach here for illegal ops. */
+ goto illegal_op;
default:
goto illegal_op;
}
@@ -10108,13 +10176,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
break;
case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
switch ((insn >> 20) & 7) {
- case 0: /* 32 x 32 -> 32, in decodetree */
+ case 0: /* 32 x 32 -> 32 */
+ case 1: /* 16 x 16 -> 32 */
+ case 3: /* 32 * 16 -> 32msb */
+ /* in decodetree */
goto illegal_op;
case 7: /* Unsigned sum of absolute differences. */
break;
- case 1: /* 16 x 16 -> 32 */
case 2: /* Dual multiply add. */
- case 3: /* 32 * 16 -> 32msb */
case 4: /* Dual multiply subtract. */
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
@@ -10126,15 +10195,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tmp = load_reg(s, rn);
tmp2 = load_reg(s, rm);
switch ((insn >> 20) & 7) {
- case 1: /* 16 x 16 -> 32 */
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
- tcg_temp_free_i32(tmp2);
- if (rs != 15) {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 2: /* Dual multiply add. */
case 4: /* Dual multiply subtract. */
if (op)
@@ -10158,23 +10218,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp2);
}
break;
- case 3: /* 32 * 16 -> 32msb */
- if (op)
- tcg_gen_sari_i32(tmp2, tmp2, 16);
- else
- gen_sxth(tmp2);
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
- tcg_gen_shri_i64(tmp64, tmp64, 16);
- tmp = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(tmp, tmp64);
- tcg_temp_free_i64(tmp64);
- if (rs != 15)
- {
- tmp2 = load_reg(s, rs);
- gen_helper_add_setq(tmp, cpu_env, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- }
- break;
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
if (rs != 15) {
@@ -10248,29 +10291,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
gen_storeq_reg(s, rs, rd, tmp64);
tcg_temp_free_i64(tmp64);
} else {
- if ((op & 0x20) || !(op & 8)) {
- /* Signed/unsigned 64-bit multiply, in decodetree */
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- goto illegal_op;
- }
- /* smlalxy */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp);
- goto illegal_op;
- }
- gen_mulxy(tmp, tmp2, op & 2, op & 1);
+ /* Signed/unsigned 64-bit multiply, in decodetree */
tcg_temp_free_i32(tmp2);
- tmp64 = tcg_temp_new_i64();
- tcg_gen_ext_i32_i64(tmp64, tmp);
tcg_temp_free_i32(tmp);
- if (op & 0x40) {
- /* 64-bit accumulate. */
- gen_addq(s, tmp64, rs, rd);
- }
- gen_storeq_reg(s, rs, rd, tmp64);
- tcg_temp_free_i64(tmp64);
+ goto illegal_op;
}
break;
}
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 7791be5590..19d12e726b 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot
@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
+@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0
MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
@@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm
QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm
QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm
QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm
+
+# Halfword multiply and multiply accumulate
+
+SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn
+SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn
+SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn
+SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn
+SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn
+SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn
+SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn
+SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn
+SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn
+SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn
+SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn
+SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn
+SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn
+SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn
+SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn
+SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 7c6226e0af..122a0537ed 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
+@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
{
@@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
+{
+ SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm
+ SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm
+ SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm
+ SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm
+}
+{
+ SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm
+ SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm
+}
+{
+ SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm
+ SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm
+}
+{
+ SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm
+ SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm
+}
+SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm
+SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm
+SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm
+SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
# Data-processing (two source registers)
--
2.17.1
next prev parent reply other threads:[~2019-08-19 21:46 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 21:36 [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-21 13:06 ` Philippe Mathieu-Daudé
2019-08-23 12:16 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-22 16:00 ` Peter Maydell
2019-08-22 17:21 ` Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-23 12:17 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-21 13:15 ` Philippe Mathieu-Daudé
2019-08-19 21:36 ` Richard Henderson [this message]
2019-08-23 12:20 ` [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-23 12:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-23 11:49 ` Peter Maydell
2019-08-23 14:22 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ Richard Henderson
2019-08-23 11:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET Richard Henderson
2019-08-23 12:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-23 12:03 ` Peter Maydell
2019-08-23 14:33 ` Richard Henderson
2019-08-27 10:32 ` Peter Maydell
2019-08-27 20:01 ` Richard Henderson
2019-08-27 22:29 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-08-23 13:04 ` Peter Maydell
2019-08-23 14:45 ` Richard Henderson
2019-08-23 14:47 ` Peter Maydell
2019-08-23 14:57 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-23 14:54 ` Peter Maydell
2019-08-23 16:24 ` Richard Henderson
2019-08-27 12:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-23 15:28 ` Peter Maydell
2019-08-23 16:28 ` Richard Henderson
2019-08-27 10:44 ` Peter Maydell
2019-08-27 10:46 ` Peter Maydell
2019-08-27 11:10 ` Peter Maydell
2019-08-27 19:35 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-23 15:39 ` Peter Maydell
2019-08-23 16:30 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-23 15:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-08-23 16:46 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-23 17:00 ` Peter Maydell
2019-08-23 17:15 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-23 17:05 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM Richard Henderson
2019-08-23 17:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-23 17:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-23 17:30 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc " Richard Henderson
2019-08-23 17:31 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-23 17:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC Richard Henderson
2019-08-21 13:21 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS Richard Henderson
2019-08-25 15:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-25 15:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-25 16:20 ` Peter Maydell
2019-08-25 17:28 ` Richard Henderson
2019-08-25 17:40 ` Richard Henderson
2019-08-25 20:43 ` Peter Maydell
2019-08-26 1:10 ` Richard Henderson
2019-08-26 1:36 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND Richard Henderson
2019-08-21 13:22 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-21 13:23 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-21 13:24 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch Richard Henderson
2019-08-25 16:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG Richard Henderson
2019-08-25 16:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT Richard Henderson
2019-08-25 16:33 ` Peter Maydell
2019-08-27 11:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-25 16:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-25 16:36 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-21 13:25 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-25 21:06 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-25 21:13 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-25 21:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-25 21:24 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-25 21:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-25 21:33 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-25 21:34 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-25 21:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-25 21:43 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-26 19:00 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract Richard Henderson
2019-08-26 19:08 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state Richard Henderson
2019-08-26 19:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-26 19:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints Richard Henderson
2019-08-26 19:37 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint Richard Henderson
2019-08-26 19:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop Richard Henderson
2019-08-26 19:44 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-26 19:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-26 20:38 ` Peter Maydell
2019-08-26 23:47 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-27 9:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-27 9:11 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-27 9:14 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches Richard Henderson
2019-08-27 9:34 ` Peter Maydell
2019-08-28 0:07 ` Richard Henderson
2019-09-03 8:23 ` Peter Maydell
2019-09-03 9:40 ` Aleksandar Markovic
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-27 9:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-27 9:39 ` Peter Maydell
2019-08-19 22:47 ` [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-27 12:28 ` Peter Maydell
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