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X-Received-From: 2607:f8b0:4864:20::b43 Subject: [Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Code generators defined using these macros rely on a helper function (as emitted by gen_helper_*). Signed-off-by: Jan Bobek --- target/i386/translate.c | 160 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/target/i386/translate.c b/target/i386/translate.c index 603a5b80a1..046914578b 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -5377,6 +5377,166 @@ INSNOP_LDST(xmm, Mhq) insnop_arg_t(opT3) arg3, insnop_arg_t(opT4) arg4, \ insnop_arg_t(opT5) arg5) +#define DEF_GEN_INSN0_HELPER(mnem, helper) \ + GEN_INSN0(mnem) \ + { \ + gen_helper_ ## helper(cpu_env); \ + } + +#define DEF_GEN_INSN2_HELPER_EPD(mnem, helper, opT1, opT2) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg2); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + } +#define DEF_GEN_INSN2_HELPER_DEP(mnem, helper, opT1, opT2) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \ + \ + tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \ + gen_helper_ ## helper(arg1, cpu_env, arg2_ptr); \ + \ + tcg_temp_free_ptr(arg2_ptr); \ + } +#ifdef TARGET_X86_64 +#define DEF_GEN_INSN2_HELPER_EPQ(mnem, helper, opT1, opT2) \ + DEF_GEN_INSN2_HELPER_EPD(mnem, helper, opT1, opT2) +#define DEF_GEN_INSN2_HELPER_QEP(mnem, helper, opT1, opT2) \ + DEF_GEN_INSN2_HELPER_DEP(mnem, helper, opT1, opT2) +#else /* !TARGET_X86_64 */ +#define DEF_GEN_INSN2_HELPER_EPQ(mnem, helper, opT1, opT2) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + g_assert_not_reached(); \ + } +#define DEF_GEN_INSN2_HELPER_QEP(mnem, helper, opT1, opT2) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + g_assert_not_reached(); \ + } +#endif /* !TARGET_X86_64 */ +#define DEF_GEN_INSN2_HELPER_EPP(mnem, helper, opT1, opT2) \ + GEN_INSN2(mnem, opT1, opT2) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \ + \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg2_ptr); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg2_ptr); \ + } + +#define DEF_GEN_INSN3_HELPER_EPD(mnem, helper, opT1, opT2, opT3) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + \ + assert(arg1 == arg2); \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg3); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + } +#ifdef TARGET_X86_64 +#define DEF_GEN_INSN3_HELPER_EPQ(mnem, helper, opT1, opT2, opT3) \ + DEF_GEN_INSN3_HELPER_EPD(mnem, helper, opT1, opT2, opT3) +#else /* !TARGET_X86_64 */ +#define DEF_GEN_INSN3_HELPER_EPQ(mnem, helper, opT1, opT2, opT3) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + g_assert_not_reached(); \ + } +#endif /* !TARGET_X86_64 */ +#define DEF_GEN_INSN3_HELPER_EPP(mnem, helper, opT1, opT2, opT3) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \ + \ + assert(arg1 == arg2); \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg3_ptr); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg3_ptr); \ + } +#define DEF_GEN_INSN3_HELPER_PPI(mnem, helper, opT1, opT2, opT3) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \ + const TCGv_i32 arg3_r32 = tcg_temp_new_i32(); \ + \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \ + tcg_gen_movi_i32(arg3_r32, arg3); \ + gen_helper_ ## helper(arg1_ptr, arg2_ptr, arg3_r32); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg2_ptr); \ + tcg_temp_free_i32(arg3_r32); \ + } +#define DEF_GEN_INSN3_HELPER_EPPI(mnem, helper, opT1, opT2, opT3) \ + GEN_INSN3(mnem, opT1, opT2, opT3) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg2_ptr = tcg_temp_new_ptr(); \ + const TCGv_i32 arg3_r32 = tcg_temp_new_i32(); \ + \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg2_ptr, cpu_env, arg2); \ + tcg_gen_movi_i32(arg3_r32, arg3); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg2_ptr, arg3_r32); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg2_ptr); \ + tcg_temp_free_i32(arg3_r32); \ + } + +#define DEF_GEN_INSN4_HELPER_PPI(mnem, helper, opT1, opT2, opT3, opT4) \ + GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \ + const TCGv_i32 arg4_r32 = tcg_temp_new_i32(); \ + \ + assert(arg1 == arg2); \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \ + tcg_gen_movi_i32(arg4_r32, arg4); \ + gen_helper_ ## helper(arg1_ptr, arg3_ptr, arg4_r32); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg3_ptr); \ + tcg_temp_free_i32(arg4_r32); \ + } +#define DEF_GEN_INSN4_HELPER_EPPI(mnem, helper, opT1, opT2, opT3, opT4) \ + GEN_INSN4(mnem, opT1, opT2, opT3, opT4) \ + { \ + const TCGv_ptr arg1_ptr = tcg_temp_new_ptr(); \ + const TCGv_ptr arg3_ptr = tcg_temp_new_ptr(); \ + const TCGv_i32 arg4_r32 = tcg_temp_new_i32(); \ + \ + assert(arg1 == arg2); \ + tcg_gen_addi_ptr(arg1_ptr, cpu_env, arg1); \ + tcg_gen_addi_ptr(arg3_ptr, cpu_env, arg3); \ + tcg_gen_movi_i32(arg4_r32, arg4); \ + gen_helper_ ## helper(cpu_env, arg1_ptr, arg3_ptr, arg4_r32); \ + \ + tcg_temp_free_ptr(arg1_ptr); \ + tcg_temp_free_ptr(arg3_ptr); \ + tcg_temp_free_i32(arg4_r32); \ + } + static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b) { enum { -- 2.20.1