From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RFC PATCH v4 35/75] target/i386: introduce instruction translator macros
Date: Wed, 21 Aug 2019 13:29:11 -0400 [thread overview]
Message-ID: <20190821172951.15333-36-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190821172951.15333-1-jan.bobek@gmail.com>
Instruction "translators" are responsible for decoding and loading
instruction operands, calling the passed-in code generator, and
storing the operands back (if applicable). Once a translator returns,
the instruction has been translated to TCG ops, hence the name.
Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
target/i386/translate.c | 272 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 272 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index eab36963c3..1c2502ff50 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5562,6 +5562,262 @@ INSNOP_LDST(xmm, Mhq)
gen_gvec_ ## gvec(arg1, arg2, arg3, arg4, ## __VA_ARGS__); \
}
+/*
+ * Instruction translators
+ */
+#define translate_insn(argc, ...) \
+ glue(translate_insn, argc)(__VA_ARGS__)
+#define translate_insn0() \
+ translate_insn_0
+#define translate_insn1(opT1) \
+ translate_insn_1 ## opT1
+#define translate_insn2(opT1, opT2) \
+ translate_insn_2 ## opT1 ## opT2
+#define translate_insn3(opT1, opT2, opT3) \
+ translate_insn_3 ## opT1 ## opT2 ## opT3
+#define translate_insn4(opT1, opT2, opT3, opT4) \
+ translate_insn_4 ## opT1 ## opT2 ## opT3 ## opT4
+#define translate_insn5(opT1, opT2, opT3, opT4, opT5) \
+ translate_insn_5 ## opT1 ## opT2 ## opT3 ## opT4 ## opT5
+#define translate_group(grpname) \
+ translate_group_ ## grpname
+
+static void translate_insn0()(
+ CPUX86State *env, DisasContext *s, int modrm,
+ CheckCpuidFeat feat, unsigned int argc_wr,
+ void (*gen_insn_fp)(CPUX86State *, DisasContext *))
+{
+ if (!check_cpuid(env, s, feat)) {
+ gen_illegal_opcode(s);
+ return;
+ }
+
+ (*gen_insn_fp)(env, s);
+}
+
+#define DEF_TRANSLATE_INSN1(opT1) \
+ static void translate_insn1(opT1)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn1_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ \
+ (*gen_insn1_fp)(env, s, arg1); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN2(opT1, opT2) \
+ static void translate_insn2(opT1, opT2)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn2_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ \
+ (*gen_insn2_fp)(env, s, arg1, arg2); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN3(opT1, opT2, opT3) \
+ static void translate_insn3(opT1, opT2, opT3)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn3_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ \
+ (*gen_insn3_fp)(env, s, arg1, arg2, arg3); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN4(opT1, opT2, opT3, opT4) \
+ static void translate_insn4(opT1, opT2, opT3, opT4)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn4_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3), insnop_arg_t(opT4))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ insnop_ctxt_t(opT4) ctxt4; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ const bool is_write4 = (4 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3) \
+ && insnop_init(opT4)(&ctxt4, env, s, modrm, is_write4)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ const insnop_arg_t(opT4) arg4 = \
+ insnop_prepare(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ \
+ (*gen_insn4_fp)(env, s, arg1, arg2, arg3, arg4); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ insnop_finalize(opT4)(&ctxt4, env, s, modrm, is_write4, arg4); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN5(opT1, opT2, opT3, opT4, opT5) \
+ static void translate_insn5(opT1, opT2, opT3, opT4, opT5)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ CheckCpuidFeat feat, unsigned int argc_wr, \
+ void (*gen_insn5_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3), insnop_arg_t(opT4), \
+ insnop_arg_t(opT5))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ insnop_ctxt_t(opT4) ctxt4; \
+ insnop_ctxt_t(opT5) ctxt5; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ const bool is_write4 = (4 <= argc_wr); \
+ const bool is_write5 = (5 <= argc_wr); \
+ \
+ if (check_cpuid(env, s, feat) \
+ && insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1) \
+ && insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2) \
+ && insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3) \
+ && insnop_init(opT4)(&ctxt4, env, s, modrm, is_write4) \
+ && insnop_init(opT5)(&ctxt5, env, s, modrm, is_write5)) { \
+ \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ const insnop_arg_t(opT4) arg4 = \
+ insnop_prepare(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ const insnop_arg_t(opT5) arg5 = \
+ insnop_prepare(opT5)(&ctxt5, env, s, modrm, is_write5); \
+ \
+ (*gen_insn5_fp)(env, s, arg1, arg2, arg3, arg4, arg5); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ insnop_finalize(opT4)(&ctxt4, env, s, modrm, is_write4, arg4); \
+ insnop_finalize(opT5)(&ctxt5, env, s, modrm, is_write5, arg5); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define OPCODE_GRP_BEGIN(grpname) \
+ static void translate_group(grpname)( \
+ CPUX86State *env, DisasContext *s, int modrm) \
+ { \
+ bool ret; \
+ insnop_ctxt_t(modrm_reg) regctxt; \
+ \
+ ret = insnop_init(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ if (ret) { \
+ const insnop_arg_t(modrm_reg) reg = \
+ insnop_prepare(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ \
+ switch (reg & 7) {
+#define OPCODE_GRPMEMB(grpname, mnem, opcode, feat, fmt, ...) \
+ case opcode: \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CHECK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ break;
+#define OPCODE_GRP_END(grpname) \
+ default: \
+ ret = false; \
+ break; \
+ } \
+ \
+ insnop_finalize(modrm_reg)(®ctxt, env, s, modrm, 0, reg); \
+ } \
+ \
+ if (!ret) { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+#include "sse-opcode.inc.h"
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
@@ -5642,6 +5898,22 @@ static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
op = x86_ldub_code(env, s);
} break;
+#define LEG(p, m, w, op) CASES(op, 3, W, w, M, m, P, p)
+#define VEX(l, p, m, w, op) CASES(op, 4, W, w, M, m, P, p, VEX_L, l)
+#define OPCODE(mnem, cases, feat, fmt, ...) \
+ cases { \
+ const int modrm = 0 < FMT_ARGC(fmt) ? x86_ldub_code(env, s) : -1; \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CHECK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ } return;
+#define OPCODE_GRP(grpname, cases) \
+ cases { \
+ const int modrm = x86_ldub_code(env, s); \
+ translate_group(grpname)(env, s, modrm); \
+ } return;
+#include "sse-opcode.inc.h"
+
default: {
if (m == M_0F38 || m == M_0F3A) {
/* rewind the advance_pc() x86_ldub_code() did */
--
2.20.1
next prev parent reply other threads:[~2019-08-21 18:18 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 17:28 [Qemu-devel] [RFC PATCH v4 00/75] rewrite MMX/SSE*/AVX/AVX2 vector instruction translation Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 01/75] target/i386: Push rex_r into DisasContext Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 02/75] target/i386: Push rex_w " Jan Bobek
2019-08-22 4:07 ` Aleksandar Markovic
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 03/75] target/i386: use dflag from DisasContext Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 04/75] target/i386: use prefix " Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 05/75] target/i386: introduce disas_insn_prefix Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 06/75] target/i386: Simplify gen_exception arguments Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 07/75] target/i386: use pc_start from DisasContext Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 08/75] target/i386: make variable b1 const Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 09/75] target/i386: make variable is_xmm const Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 10/75] target/i386: add vector register file alignment constraints Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 11/75] target/i386: introduce gen_sse_ng Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 12/75] target/i386: introduce CASES_* macros in gen_sse_ng Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 13/75] target/i386: decode the 0F38/0F3A prefix " Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 14/75] target/i386: introduce aliases for some tcg_gvec operations Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 15/75] target/i386: introduce function check_cpuid Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 16/75] target/i386: disable AVX/AVX2 cpuid bitchecks Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 17/75] target/i386: introduce instruction operand infrastructure Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 18/75] target/i386: introduce generic operand alias Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 19/75] target/i386: introduce generic either-or operand Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 20/75] target/i386: introduce generic load-store operand Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 21/75] target/i386: introduce tcg register operands Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 22/75] target/i386: introduce modrm operand Jan Bobek
2019-08-21 17:28 ` [Qemu-devel] [RFC PATCH v4 23/75] target/i386: introduce operands for decoding modrm fields Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 24/75] target/i386: introduce operand for direct-only r/m field Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 25/75] target/i386: introduce Ib (immediate) operand Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 26/75] target/i386: introduce M* (memptr) operands Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 27/75] target/i386: introduce G*, R*, E* (general register) operands Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 28/75] target/i386: introduce P*, N*, Q* (MMX) operands Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 29/75] target/i386: introduce H*, L*, V*, U*, W* (SSE/AVX) operands Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 30/75] target/i386: alias H* operands with the V* operands Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 31/75] target/i386: introduce code generators Jan Bobek
2019-08-22 4:33 ` Aleksandar Markovic
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 32/75] target/i386: introduce helper-based code generator macros Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 33/75] target/i386: introduce gvec-based " Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 34/75] target/i386: introduce sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` Jan Bobek [this message]
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 36/75] target/i386: introduce MMX translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 37/75] target/i386: introduce MMX code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 38/75] target/i386: introduce MMX vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 39/75] target/i386: introduce SSE translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 40/75] target/i386: introduce SSE code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 41/75] target/i386: introduce SSE vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 42/75] target/i386: introduce SSE2 translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 43/75] target/i386: introduce SSE2 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 44/75] target/i386: introduce SSE2 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 45/75] target/i386: introduce SSE3 translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 46/75] target/i386: introduce SSE3 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 48/75] target/i386: introduce SSSE3 translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 49/75] target/i386: introduce SSSE3 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 50/75] target/i386: introduce SSSE3 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 51/75] target/i386: introduce SSE4.1 translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 52/75] target/i386: introduce SSE4.1 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 53/75] target/i386: introduce SSE4.1 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 54/75] target/i386: introduce SSE4.2 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 55/75] target/i386: introduce SSE4.2 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 57/75] target/i386: introduce AES and PCLMULQDQ code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 58/75] target/i386: introduce AES and PCLMULQDQ vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-22 4:02 ` Aleksandar Markovic
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 59/75] target/i386: introduce AVX translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 60/75] target/i386: introduce AVX code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 61/75] target/i386: introduce AVX vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 62/75] target/i386: introduce AVX2 translators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 63/75] target/i386: introduce AVX2 code generators Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 64/75] target/i386: introduce AVX2 vector instructions to sse-opcode.inc.h Jan Bobek
2019-08-22 3:54 ` Aleksandar Markovic
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 65/75] target/i386: remove obsoleted helpers Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 66/75] target/i386: cleanup leftovers in ops_sse_header.h Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 67/75] target/i386: introduce aliases for helper-based tcg_gen_gvec_* functions Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 68/75] target/i386: convert ps((l, r)l(w, d, q), ra(w, d)) to helpers to gvec style Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 69/75] target/i386: convert pmullw/pmulhw/pmulhuw " Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 70/75] target/i386: convert pavgb/pavgw " Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 71/75] target/i386: convert pmuludq/pmaddwd " Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 72/75] target/i386: convert psadbw helper " Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 73/75] target/i386: remove obsoleted helper_mov(l, q)_mm_T0 Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 74/75] target/i386: convert pshuf(w, lw, hw, d), shuf(pd, ps) helpers to gvec style Jan Bobek
2019-08-21 17:29 ` [Qemu-devel] [RFC PATCH v4 75/75] target/i386: convert pmovmskb/movmskps/movmskpd " Jan Bobek
2019-08-21 23:53 ` Richard Henderson
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