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[222.224.160.75]) by smtp.gmail.com with ESMTPSA id y188sm13708788pfy.57.2019.08.26.21.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 21:36:26 -0700 (PDT) Date: Tue, 27 Aug 2019 13:36:24 +0900 From: Stafford Horne To: Richard Henderson Message-ID: <20190827043624.GK24874@lianli.shorne-pla.net> References: <20190827000745.19645-1-richard.henderson@linaro.org> <20190827000745.19645-7-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190827000745.19645-7-richard.henderson@linaro.org> User-Agent: Mutt/1.11.4 (2019-03-13) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: Re: [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Aug 26, 2019 at 05:07:38PM -0700, Richard Henderson wrote: > Update the CPUCFG bits to arch v1.3. > Include support for AVRP for cpu "any". > > Signed-off-by: Richard Henderson > --- > target/openrisc/cpu.h | 11 +++++++---- > target/openrisc/cpu.c | 8 ++++++-- > target/openrisc/sys_helper.c | 6 ++++++ > 3 files changed, 19 insertions(+), 6 deletions(-) > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index 18d7445e74..71c5959828 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -96,11 +96,12 @@ enum { > CPUCFGR_OF32S = (1 << 7), > CPUCFGR_OF64S = (1 << 8), > CPUCFGR_OV64S = (1 << 9), > - /* CPUCFGR_ND = (1 << 10), */ > - /* CPUCFGR_AVRP = (1 << 11), */ > + CPUCFGR_ND = (1 << 10), > + CPUCFGR_AVRP = (1 << 11), > CPUCFGR_EVBARP = (1 << 12), > - /* CPUCFGR_ISRP = (1 << 13), */ > - /* CPUCFGR_AECSRP = (1 << 14), */ > + CPUCFGR_ISRP = (1 << 13), > + CPUCFGR_AECSRP = (1 << 14), > + CPUCFGR_OF64A32S = (1 << 15), > }; > > /* DMMU configure register */ > @@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState { > > /* Fields from here on are preserved across CPU reset. */ > uint32_t vr; /* Version register */ > + uint32_t vr2; /* Version register 2 */ > + uint32_t avr; /* Architecture version register */ Do you need to update the serialization in machine.c?