From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B504C4CEC4 for ; Wed, 18 Sep 2019 15:56:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 31E8D207FC for ; Wed, 18 Sep 2019 15:56:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 31E8D207FC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcK0-0000ps-Mh for qemu-devel@archiver.kernel.org; Wed, 18 Sep 2019 11:56:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49388) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAbsM-0006xr-Ce for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAbsL-0006kQ-2a for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:14 -0400 Received: from mail-pg1-f172.google.com ([209.85.215.172]:40195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iAbsK-0006ju-P8 for qemu-devel@nongnu.org; Wed, 18 Sep 2019 11:28:12 -0400 Received: by mail-pg1-f172.google.com with SMTP id w10so40431pgj.7 for ; Wed, 18 Sep 2019 08:28:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=KCqazI/HGpARV6iRaKwxJd00KfwFI0UZc3AfbfiROjY=; b=NoU51EGqDy/heduXHcfaiF1jysSkUHT2UVavakr9Pzt8kXhP3IuVNn4UpcUTqsO5Tm UcaxiR+tNzZJ6QB1kEbIsQYI2uewCqtlMtcQyiazJfB9u/kR6JG9gKEmk35dEKEgukQ5 SNBVGA7a73WrQi/sH5e/NdEdXuoE1+nYSnWwgx9RLYGbVyT99ulNI/uq9yFcfIUPPNfY 7rhzf5bIIrsKI5YxUO9pvfFBXwfAHR1gJrbSCHhpBUIB+xWRZxgF5/3l1iM8eIDEyWY4 yIkuy23txRs60LfnXqEmAyTMQyP46By1PrDBloCo5wur07baVk3nwQHR9V+WUttGOOU9 KSZA== X-Gm-Message-State: APjAAAUDGuwYOEzdDZBbehl0EQSA8lwtwhmKmIEpgxlLHEV/Pgr1P7n1 6gJybpylL6QlnB3dzF51c4mGsg== X-Google-Smtp-Source: APXvYqyCHQNJ0TL5sGz229DHxOjSjO3GfpFHbHCXsXu+mj78TVER6BUEtdDdVL59ZDoLIKWFGCMqxQ== X-Received: by 2002:a63:ec12:: with SMTP id j18mr4437209pgh.327.1568820491407; Wed, 18 Sep 2019 08:28:11 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id d20sm10884860pfq.88.2019.09.18.08.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 08:28:10 -0700 (PDT) Date: Wed, 18 Sep 2019 07:56:11 -0700 Message-Id: <20190918145640.17349-20-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918145640.17349-1-palmer@sifive.com> References: <20190918145640.17349-1-palmer@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.215.172 Subject: [Qemu-devel] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...) in various sifive models. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 8 +++++--- hw/riscv/sifive_test.c | 5 +++-- hw/riscv/sifive_uart.c | 9 +++++---- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index 562bc3dc4c..982fbb26fd 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" +#include "qemu/log.h" #include "qemu/module.h" #include "target/riscv/cpu.h" #include "hw/hw.h" @@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_PRCI_PLLOUTDIV: return s->plloutdiv; } - hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n", + __func__, (int)addr); return 0; } @@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr, s->plloutdiv = (uint32_t) val64; break; default: - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)val64); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); } } diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index 711740939e..aa544e7428 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" +#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" #include "target/riscv/cpu.h" @@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr, break; } } - hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", - __func__, (int)addr, val64); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n", + __func__, (int)addr, val64); } static const MemoryRegionOps sifive_test_ops = { diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 9de42b1680..215990b443 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/log.h" #include "hw/sysbus.h" #include "chardev/char.h" #include "chardev/char-fe.h" @@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) return s->div; } - hw_error("%s: bad read: addr=0x%x\n", - __func__, (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); return 0; } @@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr, s->div = val64; return; } - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)value); } static const MemoryRegionOps uart_ops = { -- 2.21.0