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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.49.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/22] target/arm: Implement the GMI instruction Date: Fri, 11 Oct 2019 09:47:30 -0400 Message-Id: <20191011134744.2477-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 268c114b79..31f848ca03 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -109,3 +109,4 @@ DEF_HELPER_FLAGS_3(mte_check3, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c3edc51bba..251dfff1e1 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -254,3 +254,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 26aee0c1c9..4184d65d97 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5188,6 +5188,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; -- 2.17.1