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From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org
Cc: "Riku Voipio" <riku.voipio@iki.fi>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	qemu-devel@nongnu.org, "Emilio G. Cota" <cota@braap.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [PULL v2 30/73] atomic_template: add inline trace/plugin helpers
Date: Fri, 25 Oct 2019 07:36:30 +0100
Message-ID: <20191025063713.23374-31-alex.bennee@linaro.org> (raw)
In-Reply-To: <20191025063713.23374-1-alex.bennee@linaro.org>

From: "Emilio G. Cota" <cota@braap.org>

In preparation for plugin support.

Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.inc.c
new file mode 100644
index 00000000000..a86098fb2de
--- /dev/null
+++ b/accel/tcg/atomic_common.inc.c
@@ -0,0 +1,50 @@
+/*
+ * Common Atomic Helper Functions
+ *
+ * This file should be included before the various instantiations of
+ * the atomic_template.h helpers.
+ *
+ * Copyright (c) 2019 Linaro
+ * Written by Alex Bennée <alex.bennee@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+static inline
+void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+    CPUState *cpu = env_cpu(env);
+
+    trace_guest_mem_before_exec(cpu, addr, info);
+    trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
+}
+
+static inline void
+atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+    trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
+
+static inline
+void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+    trace_guest_mem_before_exec(env_cpu(env), addr, info);
+}
+
+static inline
+void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t info)
+{
+}
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 473d7e5a943..84d3370bf01 100644
--- a/accel/tcg/atomic_template.h
+++ b/accel/tcg/atomic_template.h
@@ -59,29 +59,6 @@
 # define ABI_TYPE  uint32_t
 #endif
 
-#define ATOMIC_TRACE_RMW do {                                           \
-        uint16_t info = glue(trace_mem_build_info_no_se, MEND)          \
-            (SHIFT, false, ATOMIC_MMU_IDX);                             \
-                                                                        \
-        trace_guest_mem_before_exec(env_cpu(env), addr, info);          \
-        trace_guest_mem_before_exec(env_cpu(env), addr,                 \
-                                    info | TRACE_MEM_ST);               \
-    } while (0)
-
-#define ATOMIC_TRACE_LD do {                                            \
-        uint16_t info = glue(trace_mem_build_info_no_se, MEND)          \
-            (SHIFT, false, ATOMIC_MMU_IDX);                             \
-                                                                        \
-        trace_guest_mem_before_exec(env_cpu(env), addr, info);          \
-    } while (0)
-
-#define ATOMIC_TRACE_ST do {                                           \
-        uint16_t info = glue(trace_mem_build_info_no_se, MEND)         \
-            (SHIFT, true, ATOMIC_MMU_IDX);                             \
-                                                                       \
-        trace_guest_mem_before_exec(env_cpu(env), addr, info);         \
-    } while (0)
-
 /* Define host-endian atomic operations.  Note that END is used within
    the ATOMIC_NAME macro, and redefined below.  */
 #if DATA_SIZE == 1
@@ -101,14 +78,17 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_RMW;
+    atomic_trace_rmw_pre(env, addr, info);
 #if DATA_SIZE == 16
     ret = atomic16_cmpxchg(haddr, cmpv, newv);
 #else
     ret = atomic_cmpxchg__nocheck(haddr, cmpv, newv);
 #endif
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_rmw_post(env, addr, info);
     return ret;
 }
 
@@ -118,10 +98,13 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_LD;
+    atomic_trace_ld_pre(env, addr, info);
     val = atomic16_read(haddr);
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_ld_post(env, addr, info);
     return val;
 }
 
@@ -130,10 +113,13 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, true,
+                                                          ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_ST;
+    atomic_trace_st_pre(env, addr, info);
     atomic16_set(haddr, val);
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_st_post(env, addr, info);
 }
 #endif
 #else
@@ -143,10 +129,13 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT, false,
+                                                          ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_RMW;
+    atomic_trace_rmw_pre(env, addr, info);
     ret = atomic_xchg__nocheck(haddr, val);
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_rmw_post(env, addr, info);
     return ret;
 }
 
@@ -157,10 +146,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                           \
     DATA_TYPE ret;                                                  \
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
+                                                           false,   \
+                                                           ATOMIC_MMU_IDX); \
                                                                     \
-    ATOMIC_TRACE_RMW;                                               \
+    atomic_trace_rmw_pre(env, addr, info);                          \
     ret = atomic_##X(haddr, val);                                   \
     ATOMIC_MMU_CLEANUP;                                             \
+    atomic_trace_rmw_post(env, addr, info);                         \
     return ret;                                                     \
 }
 
@@ -189,8 +182,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                          \
     XDATA_TYPE cmp, old, new, val = xval;                           \
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
+                                                           false,   \
+                                                           ATOMIC_MMU_IDX); \
                                                                     \
-    ATOMIC_TRACE_RMW;                                               \
+    atomic_trace_rmw_pre(env, addr, info);                          \
     smp_mb();                                                       \
     cmp = atomic_read__nocheck(haddr);                              \
     do {                                                            \
@@ -198,6 +194,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
         cmp = atomic_cmpxchg__nocheck(haddr, old, new);             \
     } while (cmp != old);                                           \
     ATOMIC_MMU_CLEANUP;                                             \
+    atomic_trace_rmw_post(env, addr, info);                         \
     return RET;                                                     \
 }
 
@@ -235,14 +232,18 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     DATA_TYPE ret;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+                                                           false,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_RMW;
+    atomic_trace_rmw_pre(env, addr, info);
 #if DATA_SIZE == 16
     ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
 #else
     ret = atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
 #endif
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_rmw_post(env, addr, info);
     return BSWAP(ret);
 }
 
@@ -252,10 +253,14 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS)
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE val, *haddr = ATOMIC_MMU_LOOKUP;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+                                                           false,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_LD;
+    atomic_trace_ld_pre(env, addr, info);
     val = atomic16_read(haddr);
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_ld_post(env, addr, info);
     return BSWAP(val);
 }
 
@@ -264,11 +269,16 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr,
 {
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+                                                           true,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_ST;
+    val = BSWAP(val);
+    atomic_trace_st_pre(env, addr, info);
     val = BSWAP(val);
     atomic16_set(haddr, val);
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_st_post(env, addr, info);
 }
 #endif
 #else
@@ -278,10 +288,14 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
     ATOMIC_MMU_DECLS;
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
     ABI_TYPE ret;
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,
+                                                           false,
+                                                           ATOMIC_MMU_IDX);
 
-    ATOMIC_TRACE_RMW;
+    atomic_trace_rmw_pre(env, addr, info);
     ret = atomic_xchg__nocheck(haddr, BSWAP(val));
     ATOMIC_MMU_CLEANUP;
+    atomic_trace_rmw_post(env, addr, info);
     return BSWAP(ret);
 }
 
@@ -292,10 +306,14 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                           \
     DATA_TYPE ret;                                                  \
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
+                                                           false,   \
+                                                           ATOMIC_MMU_IDX); \
                                                                     \
-    ATOMIC_TRACE_RMW;                                               \
+    atomic_trace_rmw_pre(env, addr, info);                          \
     ret = atomic_##X(haddr, BSWAP(val));                            \
     ATOMIC_MMU_CLEANUP;                                             \
+    atomic_trace_rmw_post(env, addr, info);                         \
     return BSWAP(ret);                                              \
 }
 
@@ -322,8 +340,11 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
     ATOMIC_MMU_DECLS;                                               \
     XDATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;                          \
     XDATA_TYPE ldo, ldn, old, new, val = xval;                      \
+    uint16_t info = glue(trace_mem_build_info_no_se, MEND)(SHIFT,   \
+                                                           false,   \
+                                                           ATOMIC_MMU_IDX); \
                                                                     \
-    ATOMIC_TRACE_RMW;                                               \
+    atomic_trace_rmw_pre(env, addr, info);                          \
     smp_mb();                                                       \
     ldn = atomic_read__nocheck(haddr);                              \
     do {                                                            \
@@ -331,6 +352,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr,       \
         ldn = atomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new));      \
     } while (ldo != ldn);                                           \
     ATOMIC_MMU_CLEANUP;                                             \
+    atomic_trace_rmw_post(env, addr, info);                         \
     return RET;                                                     \
 }
 
@@ -358,10 +380,6 @@ GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new)
 #undef MEND
 #endif /* DATA_SIZE > 1 */
 
-#undef ATOMIC_TRACE_ST
-#undef ATOMIC_TRACE_LD
-#undef ATOMIC_TRACE_RMW
-
 #undef BSWAP
 #undef ABI_TYPE
 #undef DATA_TYPE
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 82a5783a2bc..82282d30d93 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1825,6 +1825,8 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
 #define ATOMIC_MMU_CLEANUP
 #define ATOMIC_MMU_IDX   get_mmuidx(oi)
 
+#include "atomic_common.inc.c"
+
 #define DATA_SIZE 1
 #include "atomic_template.h"
 
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 8d315a65876..b09f7a15770 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -756,6 +756,8 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 #define ATOMIC_NAME(X)   HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
 #define EXTRA_ARGS
 
+#include "atomic_common.inc.c"
+
 #define DATA_SIZE 1
 #include "atomic_template.h"
 
-- 
2.20.1



  parent reply index

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-25  6:36 [PULL v2 00/73] tcg plugins and testing updates Alex Bennée
2019-10-25  6:36 ` [PULL v2 01/73] travis.yml: reduce scope of the --enable-debug build Alex Bennée
2019-10-25  6:36 ` [PULL v2 02/73] travis.yml: Add libvdeplug-dev to compile-test net/vde.c Alex Bennée
2019-10-25  6:36 ` [PULL v2 03/73] travis.yml: Use libsdl2 instead of libsdl1.2, and install libsdl2-image Alex Bennée
2019-10-25  6:36 ` [PULL v2 04/73] travis.yml: Use newer version of libgnutls and libpng Alex Bennée
2019-10-25  6:36 ` [PULL v2 05/73] travis.yml: Fix the ccache lines Alex Bennée
2019-10-25  6:36 ` [PULL v2 06/73] travis.yml: Test the release tarball Alex Bennée
2019-10-25  6:36 ` [PULL v2 07/73] travis.yml: bump Xcode 10 to latest dot release Alex Bennée
2019-10-25  6:36 ` [PULL v2 08/73] cirrus.yml: add latest Xcode build target Alex Bennée
2019-10-25  6:36 ` [PULL v2 09/73] tests/vm: netbsd autoinstall, using serial console Alex Bennée
2019-10-25  6:36 ` [PULL v2 10/73] tests/vm: Let subclasses disable IPv6 Alex Bennée
2019-10-25  6:36 ` [PULL v2 11/73] tests/vm/netbsd: Disable IPv6 Alex Bennée
2019-10-25  6:36 ` [PULL v2 12/73] travis.yml: cache the clang sanitizer build Alex Bennée
2019-10-25  6:36 ` [PULL v2 13/73] gitlab-ci.yml: Use libvdeplug-dev to compile-test the VDE network backend Alex Bennée
2019-10-25  6:36 ` [PULL v2 14/73] travis.yml: --enable-debug-tcg to check-tcg Alex Bennée
2019-10-25  6:36 ` [PULL v2 15/73] tests/docker: set HOST_ARCH if we don't have ARCH Alex Bennée
2019-10-25  6:36 ` [PULL v2 16/73] tests/docker: update Travis image to a more current version Alex Bennée
2019-10-25  6:36 ` [PULL v2 17/73] trace: expand mem_info:size_shift to 4 bits Alex Bennée
2019-10-25  6:36 ` [PULL v2 18/73] trace: add mmu_index to mem_info Alex Bennée
2019-10-25  6:36 ` [PULL v2 19/73] cpu: introduce cpu_in_exclusive_context() Alex Bennée
2019-10-25  6:36 ` [PULL v2 20/73] translate-all: use cpu_in_exclusive_work_context() in tb_flush Alex Bennée
2019-10-25  6:36 ` [PULL v2 21/73] docs/devel: add plugins.rst design document Alex Bennée
2019-10-25  6:36 ` [PULL v2 22/73] plugin: add user-facing API Alex Bennée
2019-10-25  6:36 ` [PULL v2 23/73] plugin: add core code Alex Bennée
2019-10-25  6:36 ` [PULL v2 24/73] plugin: add implementation of the api Alex Bennée
2019-10-25  6:36 ` [PULL v2 25/73] queue: add QTAILQ_REMOVE_SEVERAL Alex Bennée
2019-10-25  6:36 ` [PULL v2 26/73] cputlb: document get_page_addr_code Alex Bennée
2019-10-25  6:36 ` [PULL v2 27/73] cputlb: introduce get_page_addr_code_hostp Alex Bennée
2019-10-25  6:36 ` [PULL v2 28/73] tcg: add tcg_gen_st_ptr Alex Bennée
2019-10-25  6:36 ` [PULL v2 29/73] plugin-gen: add module for TCG-related code Alex Bennée
2019-10-25  6:36 ` Alex Bennée [this message]
2019-10-25  6:36 ` [PULL v2 31/73] tcg: let plugins instrument virtual memory accesses Alex Bennée
2019-10-25  6:36 ` [PULL v2 32/73] plugins: implement helpers for resolving hwaddr Alex Bennée
2019-10-25  6:36 ` [PULL v2 33/73] translate-all: notify plugin code of tb_flush Alex Bennée
2019-10-25  6:36 ` [PULL v2 34/73] *-user: notify plugin of exit Alex Bennée
2019-10-25  6:36 ` [PULL v2 35/73] *-user: plugin syscalls Alex Bennée
2019-10-25  6:36 ` [PULL v2 36/73] cpu: hook plugin vcpu events Alex Bennée
2019-10-25  6:36 ` [PULL v2 37/73] plugin-gen: add plugin_insn_append Alex Bennée
2019-10-25  6:36 ` [PULL v2 38/73] cputlb: ensure _cmmu helper functions follow the naming standard Alex Bennée
2019-10-25  6:36 ` [PULL v2 39/73] translator: add translator_ld{ub,sw,uw,l,q} Alex Bennée
2019-10-25  6:36 ` [PULL v2 40/73] target/arm: fetch code with translator_ld Alex Bennée
2019-10-25  6:36 ` [PULL v2 41/73] target/ppc: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 42/73] target/sh4: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 43/73] target/i386: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 44/73] target/hppa: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 45/73] target/m68k: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 46/73] target/alpha: " Alex Bennée
2019-10-25  7:40   ` USB-audio sound issues with qemu-system-ppc in Linux and Windows Howard Spoelstra
2019-10-25  6:36 ` [PULL v2 47/73] target/riscv: fetch code with translator_ld Alex Bennée
2019-10-25  6:36 ` [PULL v2 48/73] target/sparc: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 49/73] target/xtensa: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 50/73] target/openrisc: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 51/73] translator: inject instrumentation from plugins Alex Bennée
2019-10-25  6:36 ` [PULL v2 52/73] configure: add --enable-plugins Alex Bennée
2019-10-25  6:36 ` [PULL v2 53/73] plugin: add API symbols to qemu-plugins.symbols Alex Bennée
2019-10-25  6:36 ` [PULL v2 54/73] plugin: expand the plugin_init function to include an info block Alex Bennée
2019-10-25  6:36 ` [PULL v2 55/73] plugin: add qemu_plugin_insn_disas helper Alex Bennée
2019-10-25  6:36 ` [PULL v2 56/73] plugin: add qemu_plugin_outs helper Alex Bennée
2019-10-25  6:36 ` [PULL v2 57/73] vl: support -plugin option Alex Bennée
2019-10-25  6:36 ` [PULL v2 58/73] linux-user: " Alex Bennée
2019-10-25  6:36 ` [PULL v2 59/73] tests/plugin: add sample plugins Alex Bennée
2019-10-25  6:37 ` [PULL v2 60/73] tests/tcg/Makefile.target: fix path to config-host.mak Alex Bennée
2019-10-25  6:37 ` [PULL v2 61/73] tests/tcg: set QEMU_OPTS for all cris runs Alex Bennée
2019-10-25  6:37 ` [PULL v2 62/73] tests/tcg: move "virtual" tests to EXTRA_TESTS Alex Bennée
2019-10-25  6:37 ` [PULL v2 63/73] tests/tcg: drop test-i386-fprem from TESTS when not SLOW Alex Bennée
2019-10-25  6:37 ` [PULL v2 64/73] tests/tcg: enable plugin testing Alex Bennée
2019-10-25  6:37 ` [PULL v2 65/73] tests/plugin: add a hotblocks plugin Alex Bennée
2019-10-25  6:37 ` [PULL v2 66/73] tests/plugin: add instruction execution breakdown Alex Bennée
2019-10-25  6:37 ` [PULL v2 67/73] tests/plugin: add hotpages to analyse memory access patterns Alex Bennée
2019-10-25  6:37 ` [PULL v2 68/73] accel/stubs: reduce headers from tcg-stub Alex Bennée
2019-10-25  6:37 ` [PULL v2 69/73] include/exec: wrap cpu_ldst.h in CONFIG_TCG Alex Bennée
2019-10-25  6:37 ` [PULL v2 70/73] .travis.yml: add --enable-plugins tests Alex Bennée
2019-10-25  6:37 ` [PULL v2 71/73] scripts/checkpatch.pl: don't complain about (foo, /* empty */) Alex Bennée
2019-10-25  6:37 ` [PULL v2 72/73] MAINTAINERS: add me for the TCG plugins code Alex Bennée
2019-10-25  6:37 ` [PULL v2 73/73] travis.yml: enable linux-gcc-debug-tcg cache Alex Bennée
2019-10-25 12:59 ` [PULL v2 00/73] tcg plugins and testing updates Markus Armbruster
2019-10-25 15:04   ` Alex Bennée
2019-10-25 20:23     ` Markus Armbruster
2019-10-27 19:44       ` Peter Maydell
2019-10-28  9:07         ` Alex Bennée
2019-11-06 12:42       ` Markus Armbruster
2019-11-08 17:23         ` Peter Maydell
2019-10-25 16:53 ` Peter Maydell
2019-10-25 19:38   ` Alex Bennée

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  git send-email \
    --in-reply-to=20191025063713.23374-31-alex.bennee@linaro.org \
    --to=alex.bennee@linaro.org \
    --cc=cota@braap.org \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=riku.voipio@iki.fi \
    --cc=rth@twiddle.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git