From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Stefan Weil <sw@weilnetz.de>
Subject: [PULL 01/12] tci: Add implementation for INDEX_op_ld16u_i64
Date: Fri, 25 Oct 2019 10:21:48 -0400 [thread overview]
Message-ID: <20191025142159.12459-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20191025142159.12459-1-richard.henderson@linaro.org>
From: Stefan Weil <sw@weilnetz.de>
This fixes "make check-tcg" on a Debian x86_64 host.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190410194838.10123-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/tcg/tci.c b/tcg/tci.c
index 33edca1903..a6208653e8 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -127,6 +127,12 @@ static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
tci_write_reg(regs, index, value);
}
+static void
+tci_write_reg16(tcg_target_ulong *regs, TCGReg index, uint16_t value)
+{
+ tci_write_reg(regs, index, value);
+}
+
static void
tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value)
{
@@ -585,6 +591,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i32:
+ TODO();
+ break;
case INDEX_op_ld16u_i32:
TODO();
break;
@@ -854,7 +862,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2));
break;
case INDEX_op_ld8s_i64:
+ TODO();
+ break;
case INDEX_op_ld16u_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_r(regs, &tb_ptr);
+ t2 = tci_read_s32(&tb_ptr);
+ tci_write_reg16(regs, t0, *(uint16_t *)(t1 + t2));
+ break;
case INDEX_op_ld16s_i64:
TODO();
break;
--
2.17.1
next prev parent reply other threads:[~2019-10-25 14:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 14:21 [PULL 00/12] tcg patch queue Richard Henderson
2019-10-25 14:21 ` Richard Henderson [this message]
2019-10-25 14:21 ` [PULL 02/12] cputlb: ensure _cmmu helper functions follow the naming standard Richard Henderson
2019-10-25 14:21 ` [PULL 03/12] cpu: use ROUND_UP() to define xxx_PAGE_ALIGN Richard Henderson
2019-10-25 14:21 ` [PULL 04/12] exec: Split out variable page size support to exec-vary.c Richard Henderson
2019-10-25 14:21 ` [PULL 05/12] configure: Detect compiler support for __attribute__((alias)) Richard Henderson
2019-10-25 14:21 ` [PULL 06/12] exec: Use const alias for TARGET_PAGE_BITS_VARY Richard Henderson
2019-10-25 14:21 ` [PULL 07/12] exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG Richard Henderson
2019-10-25 14:21 ` [PULL 08/12] exec: Promote TARGET_PAGE_MASK to target_long Richard Henderson
2019-10-25 14:21 ` [PULL 09/12] exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY Richard Henderson
2019-10-25 14:21 ` [PULL 10/12] cputlb: Fix tlb_vaddr_to_host Richard Henderson
2019-10-25 14:21 ` [PULL 11/12] translate-all: fix uninitialized tb->orig_tb Richard Henderson
2019-10-25 14:21 ` [PULL 12/12] translate-all: Remove tb_alloc Richard Henderson
2019-10-25 16:12 ` [PULL 00/12] tcg patch queue Peter Maydell
2019-10-25 20:48 ` Richard Henderson
2019-10-26 11:04 ` no-reply
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