From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Eric Blake <eblake@redhat.com>, qemu-devel@nongnu.org
Cc: "Kevin Wolf" <kwolf@redhat.com>,
"Stefan Hajnoczi" <stefanha@redhat.com>,
qemu-block@nongnu.org, qemu-trivial@nongnu.org,
"Max Reitz" <mreitz@redhat.com>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@rt-rk.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v4 2/2] hw/mips/gt64xxx: Remove dynamic field width from trace events
Date: Mon, 18 Nov 2019 23:27:46 +0100 [thread overview]
Message-ID: <20191118222746.31467-3-philmd@redhat.com> (raw)
In-Reply-To: <20191118222746.31467-1-philmd@redhat.com>
Since not all trace backends support dynamic field width in
format (dtrace via stap does not), replace by a static field
width instead.
We previously passed to the trace API 'width << 1' as the number
of hex characters to display (the dynamic field width). We don't
need this anymore. Instead, display the size of bytes accessed.
Fixes: ab6bff424f (gt64xxx_pci: Convert debug printf to trace events)
Reported-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Buglink: https://bugs.launchpad.net/qemu/+bug/1844817
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: Do not update qemu_log_mask()
v3: display size (in byte)
v4: added Fixes/Reviewed-by
---
hw/mips/gt64xxx_pci.c | 16 ++++++++--------
hw/mips/trace-events | 4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 5cab9c1ee1..f1af840d8e 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -642,19 +642,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
- trace_gt64120_write("INTRCAUSE", size << 1, val);
+ trace_gt64120_write("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
- trace_gt64120_write("INTRMASK", size << 1, val);
+ trace_gt64120_write("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
- trace_gt64120_write("ICMASK", size << 1, val);
+ trace_gt64120_write("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
- trace_gt64120_write("SERR0MASK", size << 1, val);
+ trace_gt64120_write("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@@ -930,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
- trace_gt64120_read("INTRCAUSE", size << 1, val);
+ trace_gt64120_read("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
- trace_gt64120_read("INTRMASK", size << 1, val);
+ trace_gt64120_read("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
- trace_gt64120_read("ICMASK", size << 1, val);
+ trace_gt64120_read("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
- trace_gt64120_read("SERR0MASK", size << 1, val);
+ trace_gt64120_read("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
diff --git a/hw/mips/trace-events b/hw/mips/trace-events
index 75d4c73f2e..321933283f 100644
--- a/hw/mips/trace-events
+++ b/hw/mips/trace-events
@@ -1,4 +1,4 @@
# gt64xxx.c
-gt64120_read(const char *regname, int width, uint64_t value) "gt64120 read %s value:0x%0*" PRIx64
-gt64120_write(const char *regname, int width, uint64_t value) "gt64120 write %s value:0x%0*" PRIx64
+gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
+gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
--
2.21.0
next prev parent reply other threads:[~2019-11-18 22:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 22:27 [PATCH v4 0/2] hw: Remove dynamic field width from trace events Philippe Mathieu-Daudé
2019-11-18 22:27 ` [PATCH v4 1/2] hw/block/pflash: " Philippe Mathieu-Daudé
2019-11-18 22:27 ` Philippe Mathieu-Daudé [this message]
2019-11-18 22:29 ` [PATCH-for-4.2 v4 0/2] hw: " Philippe Mathieu-Daudé
2019-11-19 16:21 ` [PATCH " Stefan Hajnoczi
2019-11-19 16:24 ` Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191118222746.31467-3-philmd@redhat.com \
--to=philmd@redhat.com \
--cc=aleksandar.rikalo@rt-rk.com \
--cc=amarkovic@wavecomp.com \
--cc=aurelien@aurel32.net \
--cc=eblake@redhat.com \
--cc=kwolf@redhat.com \
--cc=mreitz@redhat.com \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-trivial@nongnu.org \
--cc=stefanha@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).