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[79.176.6.42]) by smtp.gmail.com with ESMTPSA id 40sm12003083qtc.95.2019.11.19.03.05.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2019 03:05:16 -0800 (PST) Date: Tue, 19 Nov 2019 06:05:11 -0500 From: "Michael S. Tsirkin" To: qi1.zhang@intel.com Subject: Re: [PATCH v2 0/2] TM field check failed Message-ID: <20191119060259-mutt-send-email-mst@kernel.org> References: MIME-Version: 1.0 In-Reply-To: X-MC-Unique: 4JcX_BvQO7-o-BTGLHt6gg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, qemu-devel@nongnu.org, peterx@redhat.com, pbonzini@redhat.com, yadong.qi@intel.com, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zhang@intel.com wrote: > From: "Zhang, Qi" >=20 > spilt the reserved fields arrays and remove TM field from reserved=20 > bits Looks good to me. Also Cc Peter Xu. Also I wonder - do we need to version this change with the machine type? Peter what's your take? Also, Peter, how about we create a MAINTAINERS entry for IOMMUs and add everyone involved, this way people will remember to CC you? > Changelog V1: > add descriptons > Changelog V2: > refine >=20 > Zhang, Qi (2): > intel_iommu: split the resevred fields arrays into two ones > intel_iommu: TM field should not be in reserved bits >=20 > hw/i386/intel_iommu.c | 35 ++++++++++++++++++++-------------- > hw/i386/intel_iommu_internal.h | 17 +++++++++++++---- > 2 files changed, 34 insertions(+), 18 deletions(-) >=20 > --=20 > 2.20.1