From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 2/4] hw/arm: versal: Add the CRP as unimplemented
Date: Tue, 26 Nov 2019 14:12:37 +0000 [thread overview]
Message-ID: <20191126141239.8219-3-peter.maydell@linaro.org> (raw)
In-Reply-To: <20191126141239.8219-1-peter.maydell@linaro.org>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the CRP as unimplemented thus avoiding bus errors when
guests access these registers.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-versal.h | 3 +++
hw/arm/xlnx-versal.c | 2 ++
2 files changed, 5 insertions(+)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 14405c1465d..d844c4ffe47 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -119,4 +119,7 @@ typedef struct Versal {
#define MM_IOU_SCNTRS_SIZE 0x10000
#define MM_FPD_CRF 0xfd1a0000U
#define MM_FPD_CRF_SIZE 0x140000
+
+#define MM_PMC_CRP 0xf1260000U
+#define MM_PMC_CRP_SIZE 0x10000
#endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 98163eb1aad..8b3d8d85b86 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -257,6 +257,8 @@ static void versal_unimp(Versal *s)
MM_CRL, MM_CRL_SIZE);
versal_unimp_area(s, "crf", &s->mr_ps,
MM_FPD_CRF, MM_FPD_CRF_SIZE);
+ versal_unimp_area(s, "crp", &s->mr_ps,
+ MM_PMC_CRP, MM_PMC_CRP_SIZE);
versal_unimp_area(s, "iou-scntr", &s->mr_ps,
MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE);
versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps,
--
2.20.1
next prev parent reply other threads:[~2019-11-26 14:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-26 14:12 [PULL 0/4] target-arm queue Peter Maydell
2019-11-26 14:12 ` [PULL 1/4] target/arm: Fix handling of cortex-m FTYPE flag in EXCRET Peter Maydell
2019-11-26 14:12 ` Peter Maydell [this message]
2019-11-26 14:12 ` [PULL 3/4] target/arm: Fix ISR_EL1 tracking when executing at EL2 Peter Maydell
2019-11-26 14:12 ` [PULL 4/4] target/arm: Honor HCR_EL2.TID3 trapping requirements Peter Maydell
2019-11-26 19:47 ` [PULL 0/4] target-arm queue Peter Maydell
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