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[34.244.242.0]) by smtp.gmail.com with ESMTPSA id n1sm12274254wrw.52.2019.12.02.06.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:06:57 -0800 (PST) Date: Mon, 2 Dec 2019 15:07:00 +0100 From: "Edgar E. Iglesias" To: Marc Zyngier Subject: Re: [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers Message-ID: <20191202140700.GF25295@toto> References: <20191201122018.25808-1-maz@kernel.org> <20191201122018.25808-6-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191201122018.25808-6-maz@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Peter Maydell , Richard Henderson , qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Dec 01, 2019 at 12:20:18PM +0000, Marc Zyngier wrote: > QEMU lacks the minimum Jazelle implementation that is required > by the architecture (everything is RAZ or RAZ/WI). Add it > together with the HCR_EL2.TID0 trapping that goes with it. Looks good to me: Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Marc Zyngier > --- > target/arm/helper.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0ba08d550a..d6fc198a97 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6040,6 +6040,16 @@ static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, > return CP_ACCESS_OK; > } > > +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo *ri, > + bool isread) > +{ > + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID0)) { > + return CP_ACCESS_TRAP_EL2; > + } > + > + return CP_ACCESS_OK; > +} > + > void register_cp_regs_for_features(ARMCPU *cpu) > { > /* Register all the coprocessor registers based on feature bits */ > @@ -6057,6 +6067,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) > define_arm_cp_regs(cpu, not_v8_cp_reginfo); > } > > + if (cpu_isar_feature(jazelle, cpu)) { > + ARMCPRegInfo jazelle_regs[] = { > + { .name = "JIDR", > + .cp = 14, .crn = 0, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_R, .accessfn = access_jazelle, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "JOSCR", > + .cp = 14, .crn = 1, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "JMCR", > + .cp = 14, .crn = 2, .crm = 0, .opc1 = 7, .opc2 = 0, > + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + REGINFO_SENTINEL > + }; > + > + define_arm_cp_regs(cpu, jazelle_regs); > + } > if (arm_feature(env, ARM_FEATURE_V6)) { > /* The ID registers all have impdef reset values */ > ARMCPRegInfo v6_idregs[] = { > -- > 2.20.1 > >