From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>
Subject: [PATCH v5 15/22] tests/tcg/aarch64: userspace system register test
Date: Tue, 14 Jan 2020 15:09:46 +0000 [thread overview]
Message-ID: <20200114150953.27659-16-alex.bennee@linaro.org> (raw)
In-Reply-To: <20200114150953.27659-1-alex.bennee@linaro.org>
This tests a bunch of registers that the kernel allows userspace to
read including the CPUID registers. We need a SVE aware compiler as we
are testing the id_aa64zfr0_el1 register in the set.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20190205190224.2198-7-alex.bennee@linaro.org>
---
vgdbstub
- don't build unless using docker or CROSS_CC_HAS_SVE
---
tests/tcg/aarch64/sysregs.c | 172 ++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 6 ++
2 files changed, 178 insertions(+)
create mode 100644 tests/tcg/aarch64/sysregs.c
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
new file mode 100644
index 0000000000..40cf8d2877
--- /dev/null
+++ b/tests/tcg/aarch64/sysregs.c
@@ -0,0 +1,172 @@
+/*
+ * Check emulated system register access for linux-user mode.
+ *
+ * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt
+ *
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <asm/hwcap.h>
+#include <stdio.h>
+#include <sys/auxv.h>
+#include <signal.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifndef HWCAP_CPUID
+#define HWCAP_CPUID (1 << 11)
+#endif
+
+int failed_bit_count;
+
+/* Read and print system register `id' value */
+#define get_cpu_reg(id) ({ \
+ unsigned long __val = 0xdeadbeef; \
+ asm("mrs %0, "#id : "=r" (__val)); \
+ printf("%-20s: 0x%016lx\n", #id, __val); \
+ __val; \
+ })
+
+/* As above but also check no bits outside of `mask' are set*/
+#define get_cpu_reg_check_mask(id, mask) ({ \
+ unsigned long __cval = get_cpu_reg(id); \
+ unsigned long __extra = __cval & ~mask; \
+ if (__extra) { \
+ printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \
+ failed_bit_count++; \
+ } \
+})
+
+/* As above but check RAZ */
+#define get_cpu_reg_check_zero(id) ({ \
+ unsigned long __val = 0xdeadbeef; \
+ asm("mrs %0, "#id : "=r" (__val)); \
+ if (__val) { \
+ printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \
+ failed_bit_count++; \
+ } \
+})
+
+/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */
+#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL)
+
+bool should_fail;
+int should_fail_count;
+int should_not_fail_count;
+uintptr_t failed_pc[10];
+
+void sigill_handler(int signo, siginfo_t *si, void *data)
+{
+ ucontext_t *uc = (ucontext_t *)data;
+
+ if (should_fail) {
+ should_fail_count++;
+ } else {
+ uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc;
+ failed_pc[should_not_fail_count++] = pc;
+ }
+ uc->uc_mcontext.pc += 4;
+}
+
+int main(void)
+{
+ struct sigaction sa;
+
+ /* Hook in a SIGILL handler */
+ memset(&sa, 0, sizeof(struct sigaction));
+ sa.sa_flags = SA_SIGINFO;
+ sa.sa_sigaction = &sigill_handler;
+ sigemptyset(&sa.sa_mask);
+
+ if (sigaction(SIGILL, &sa, 0) != 0) {
+ perror("sigaction");
+ return 1;
+ }
+
+ /* Counter values have been exposed since Linux 4.12 */
+ printf("Checking Counter registers\n");
+
+ get_cpu_reg(ctr_el0);
+ get_cpu_reg(cntvct_el0);
+ get_cpu_reg(cntfrq_el0);
+
+ /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */
+ if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
+ printf("CPUID registers unavailable\n");
+ return 1;
+ } else {
+ printf("Checking CPUID registers\n");
+ }
+
+ /*
+ * Some registers only expose some bits to user-space. Anything
+ * that is IMPDEF is exported as 0 to user-space. The _mask checks
+ * assert no extra bits are set.
+ *
+ * This check is *not* comprehensive as some fields are set to
+ * minimum valid fields - for the purposes of this check allowed
+ * to have non-zero values.
+ */
+ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
+ get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
+ /* TGran4 & TGran64 as pegged to -1 */
+ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
+ get_cpu_reg_check_zero(id_aa64mmfr1_el1);
+ /* EL1/EL0 reported as AA64 only */
+ get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
+ get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
+ /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
+ get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
+ get_cpu_reg_check_zero(id_aa64dfr1_el1);
+ get_cpu_reg_check_zero(id_aa64zfr0_el1);
+
+ get_cpu_reg_check_zero(id_aa64afr0_el1);
+ get_cpu_reg_check_zero(id_aa64afr1_el1);
+
+ get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff));
+ /* mpidr sets bit 31, everything else hidden */
+ get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000));
+ /* REVIDR is all IMPDEF so should be all zeros to user-space */
+ get_cpu_reg_check_zero(revidr_el1);
+
+ /*
+ * There are a block of more registers that are RAZ in the rest of
+ * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for
+ * brevity we don't check stuff that is currently un-allocated
+ * here. Feel free to add them ;-)
+ */
+
+ printf("Remaining registers should fail\n");
+ should_fail = true;
+
+ /* Unexposed register access causes SIGILL */
+ get_cpu_reg(id_mmfr0_el1);
+ get_cpu_reg(id_mmfr1_el1);
+ get_cpu_reg(id_mmfr2_el1);
+ get_cpu_reg(id_mmfr3_el1);
+
+ get_cpu_reg(mvfr0_el1);
+ get_cpu_reg(mvfr1_el1);
+
+ if (should_not_fail_count > 0) {
+ int i;
+ for (i = 0; i < should_not_fail_count; i++) {
+ uintptr_t pc = failed_pc[i];
+ uint32_t insn = *(uint32_t *) pc;
+ printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc);
+ }
+ return 1;
+ }
+
+ if (failed_bit_count > 0) {
+ printf("Extra information leaked to user-space!\n");
+ return 1;
+ }
+
+ return should_fail_count == 6 ? 0 : 1;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index df3fe8032c..afcbd06467 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -39,4 +39,10 @@ run-semiconsole: semiconsole
run-plugin-semiconsole-with-%:
$(call skip-test, $<, "MANUAL ONLY")
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE),)
+# System Registers Tests
+AARCH64_TESTS += sysregs
+sysregs: CFLAGS+=-march=armv8.1-a+sve
+endif
+
TESTS += $(AARCH64_TESTS)
--
2.20.1
next prev parent reply other threads:[~2020-01-14 15:31 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-14 15:09 [PATCH v5 00/22] gdbstub refactor and SVE support (+check-tcg tweaks) Alex Bennée
2020-01-14 15:09 ` [PATCH v5 01/22] gdbstub: make GDBState static and have common init function Alex Bennée
2020-01-14 15:09 ` [PATCH v5 02/22] gdbstub: stop passing GDBState * around and use global Alex Bennée
2020-01-16 10:05 ` Damien Hedde
2020-01-16 15:07 ` Philippe Mathieu-Daudé
2020-01-14 15:09 ` [PATCH v5 03/22] gdbstub: move str_buf to GDBState and use GString Alex Bennée
2020-01-14 15:09 ` [PATCH v5 04/22] gdbstub: move mem_buf to GDBState and use GByteArray Alex Bennée
2020-01-14 15:09 ` [PATCH v5 05/22] gdbstub: add helper for 128 bit registers Alex Bennée
2020-01-14 15:09 ` [PATCH v5 06/22] target/arm: use gdb_get_reg helpers Alex Bennée
2020-01-14 15:09 ` [PATCH v5 07/22] target/m68k: " Alex Bennée
2020-01-14 15:09 ` [PATCH v5 08/22] gdbstub: extend GByteArray to read register helpers Alex Bennée
2020-01-15 5:53 ` David Gibson
2020-01-16 9:58 ` Damien Hedde
2020-01-14 15:09 ` [PATCH v5 09/22] target/arm: prepare for multiple dynamic XMLs Alex Bennée
2020-01-15 22:21 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 10/22] target/arm: explicitly encode regnum in our XML Alex Bennée
2020-01-14 15:09 ` [PATCH v5 11/22] target/arm: default SVE length to 64 bytes for linux-user Alex Bennée
2020-01-14 15:09 ` [PATCH v5 12/22] target/arm: generate xml description of our SVE registers Alex Bennée
2020-01-15 22:16 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 13/22] tests/tcg: add a configure compiler check for ARMv8.1 and SVE Alex Bennée
2020-01-15 22:24 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 14/22] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY Alex Bennée
2020-01-14 15:09 ` Alex Bennée [this message]
2020-01-15 22:30 ` [PATCH v5 15/22] tests/tcg/aarch64: userspace system register test Richard Henderson
2020-01-14 15:09 ` [PATCH v5 16/22] configure: allow user to specify what gdb to use Alex Bennée
2020-01-15 22:31 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 17/22] tests/guest-debug: add a simple test runner Alex Bennée
2020-01-15 22:40 ` Richard Henderson
2020-01-15 22:43 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 18/22] tests/tcg/aarch64: add a gdbstub testcase for SVE registers Alex Bennée
2020-01-15 22:54 ` Richard Henderson
2020-01-16 7:36 ` Alex Bennée
2020-01-14 15:09 ` [PATCH v5 19/22] tests/tcg/aarch64: add SVE iotcl test Alex Bennée
2020-01-15 22:46 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 20/22] tests/tcg/aarch64: add test-sve-ioctl guest-debug test Alex Bennée
2020-01-15 23:07 ` Richard Henderson
2020-02-04 21:45 ` Alex Bennée
2020-02-05 10:19 ` Richard Henderson
2020-02-05 11:49 ` Andrew Jones
2020-01-14 15:09 ` [PATCH v5 21/22] gdbstub: change GDBState.last_packet to GByteArray Alex Bennée
2020-01-15 23:10 ` Richard Henderson
2020-01-14 15:09 ` [PATCH v5 22/22] gdbstub: do not split gdb_monitor_write payload Alex Bennée
2020-01-15 23:11 ` Richard Henderson
2020-01-14 18:57 ` [PATCH v5 00/22] gdbstub refactor and SVE support (+check-tcg tweaks) no-reply
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