From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, alex.bennee@linaro.org
Subject: [PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO
Date: Sat, 8 Feb 2020 12:57:56 +0000 [thread overview]
Message-ID: <20200208125816.14954-1-richard.henderson@linaro.org> (raw)
Based-on: https://git.linaro.org/people/peter.maydell/qemu-arm.git/log/?h=target-arm.next
Version 4 incorporates the feedback on v3. In particular:
* Split out CPSR_J masking to its own patch.
* Merge trivial braces formatting fixes into patch 5.
* Drop "Tidy msr_mask" patch, leaving CPSR_USER handling alone.
* Fixes for EL3 in "Set PAN bit as required on exception entry".
Patches without review:
0005-target-arm-Split-out-aarch32_cpsr_valid_mask.patch
0006-target-arm-Mask-CPSR_J-when-Jazelle-is-not-enable.patch
0009-target-arm-Remove-CPSR_RESERVED.patch
0014-target-arm-Set-PAN-bit-as-required-on-exception-e.patch
r~
Richard Henderson (20):
target/arm: Add arm_mmu_idx_is_stage1_of_2
target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled
target/arm: Add isar_feature tests for PAN + ATS1E1
target/arm: Move LOR regdefs to file scope
target/arm: Split out aarch32_cpsr_valid_mask
target/arm: Mask CPSR_J when Jazelle is not enabled
target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask
target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return
target/arm: Remove CPSR_RESERVED
target/arm: Introduce aarch64_pstate_valid_mask
target/arm: Update MSR access for PAN
target/arm: Update arm_mmu_idx_el for PAN
target/arm: Enforce PAN semantics in get_S1prot
target/arm: Set PAN bit as required on exception entry
target/arm: Implement ATS1E1 system registers
target/arm: Enable ARMv8.2-ATS1E1 in -cpu max
target/arm: Add ID_AA64MMFR2_EL1
target/arm: Update MSR access to UAO
target/arm: Implement UAO semantics
target/arm: Enable ARMv8.2-UAO in -cpu max
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 95 ++++++++---
target/arm/internals.h | 85 ++++++++++
target/arm/cpu.c | 4 +
target/arm/cpu64.c | 9 +
target/arm/helper-a64.c | 6 +-
target/arm/helper.c | 327 +++++++++++++++++++++++++++++--------
target/arm/kvm64.c | 2 +
target/arm/op_helper.c | 14 +-
target/arm/translate-a64.c | 31 ++++
target/arm/translate.c | 42 +++--
11 files changed, 499 insertions(+), 118 deletions(-)
--
2.20.1
next reply other threads:[~2020-02-08 12:59 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-08 12:57 Richard Henderson [this message]
2020-02-08 12:57 ` [PATCH v4 01/20] target/arm: Add arm_mmu_idx_is_stage1_of_2 Richard Henderson
2020-02-08 12:57 ` [PATCH v4 02/20] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Richard Henderson
2020-02-08 12:57 ` [PATCH v4 03/20] target/arm: Add isar_feature tests for PAN + ATS1E1 Richard Henderson
2020-02-14 11:28 ` Peter Maydell
2020-02-14 16:20 ` Peter Maydell
2020-02-14 18:19 ` Richard Henderson
2020-02-08 12:58 ` [PATCH v4 04/20] target/arm: Move LOR regdefs to file scope Richard Henderson
2020-02-08 12:58 ` [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask Richard Henderson
2020-02-11 18:06 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 06/20] target/arm: Mask CPSR_J when Jazelle is not enabled Richard Henderson
2020-02-11 18:07 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 07/20] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Richard Henderson
2020-02-08 12:58 ` [PATCH v4 08/20] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Richard Henderson
2020-02-08 12:58 ` [PATCH v4 09/20] target/arm: Remove CPSR_RESERVED Richard Henderson
2020-02-11 18:07 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 10/20] target/arm: Introduce aarch64_pstate_valid_mask Richard Henderson
2020-02-08 12:58 ` [PATCH v4 11/20] target/arm: Update MSR access for PAN Richard Henderson
2020-02-08 12:58 ` [PATCH v4 12/20] target/arm: Update arm_mmu_idx_el " Richard Henderson
2020-02-08 12:58 ` [PATCH v4 13/20] target/arm: Enforce PAN semantics in get_S1prot Richard Henderson
2020-02-08 12:58 ` [PATCH v4 14/20] target/arm: Set PAN bit as required on exception entry Richard Henderson
2020-02-11 18:09 ` Peter Maydell
2020-02-08 12:58 ` [PATCH v4 15/20] target/arm: Implement ATS1E1 system registers Richard Henderson
2020-02-08 12:58 ` [PATCH v4 16/20] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Richard Henderson
2020-02-08 12:58 ` [PATCH v4 17/20] target/arm: Add ID_AA64MMFR2_EL1 Richard Henderson
2020-02-08 12:58 ` [PATCH v4 18/20] target/arm: Update MSR access to UAO Richard Henderson
2020-02-08 12:58 ` [PATCH v4 19/20] target/arm: Implement UAO semantics Richard Henderson
2020-02-08 12:58 ` [PATCH v4 20/20] target/arm: Enable ARMv8.2-UAO in -cpu max Richard Henderson
2020-02-11 18:41 ` [PATCH v4 00/20] target/arm: Implement PAN, ATS1E1, UAO Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200208125816.14954-1-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).